SKL: Release v58 event files

This commit releases SKL v58 events and updates mapfile.csv
accordingly.

SKL/events/skylake_core.json

@@ -2,7 +2,7 @@
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
     "Info": "Performance Monitoring Events for 6th Generation Intel(R) Core(TM) Processor - V58",
-    "DatePublished": "01/09/2024",
+    "DatePublished": "02/22/2024",
     "Version": "58",
     "Legend": ""
   },
@@ -2403,8 +2403,8 @@
       "EventCode": "0x79",
       "UMask": "0x18",
       "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
-      "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops [This event is alias to IDQ.DSB_CYCLES_OK]",
-      "PublicDescription": "Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.DSB_CYCLES_OK]",
+      "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is alias to IDQ.DSB_CYCLES_OK]",
+      "PublicDescription": "Counts the number of cycles 4 or more uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.DSB_CYCLES_OK]",
       "Counter": "0,1,2,3",
       "CounterHTOff": "0,1,2,3,4,5,6,7",
       "SampleAfterValue": "2000003",
@@ -2449,8 +2449,8 @@
       "EventCode": "0x79",
       "UMask": "0x18",
       "EventName": "IDQ.DSB_CYCLES_OK",
-      "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS]",
-      "PublicDescription": "Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS]",
+      "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS]",
+      "PublicDescription": "Counts the number of cycles 4 or more uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS]",
       "Counter": "0,1,2,3",
       "CounterHTOff": "0,1,2,3,4,5,6,7",
       "SampleAfterValue": "2000003",
@@ -3830,7 +3830,7 @@
       "UMask": "0x01",
       "EventName": "DSB2MITE_SWITCHES.COUNT",
       "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
-      "PublicDescription": "This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses.\nNote: Invoking MITE requires two or three cycles delay.",
+      "PublicDescription": "This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses. Note: Invoking MITE requires two or three cycles delay.",
       "Counter": "0,1,2,3",
       "CounterHTOff": "0,1,2,3,4,5,6,7",
       "SampleAfterValue": "2000003",

SKL/events/skylake_fp_arith_inst.json

@@ -2,7 +2,7 @@
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
     "Info": "Performance Monitoring Events for 6th Generation Intel(R) Core(TM) Processor - V58",
-    "DatePublished": "01/09/2024",
+    "DatePublished": "02/22/2024",
     "Version": "58",
     "Legend": ""
   },

SKL/events/skylake_uncore.json

@@ -2,7 +2,7 @@
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
     "Info": "Performance Monitoring Events for 6th Generation Intel(R) Core(TM) Processor - V58",
-    "DatePublished": "01/09/2024",
+    "DatePublished": "02/22/2024",
     "Version": "58",
     "Legend": ""
   },