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ICL: Release v1.19 event files
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This commit releases ICL v1.19 events and updates mapfile.csv
accordingly.
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@edwarddavidbaker
edwarddavidbaker committed Jun 12, 2023
1 parent e4f8353 commit f3d8411
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Showing 4 changed files with 103 additions and 31 deletions.
104 changes: 88 additions & 16 deletions ICL/events/icelake_core.json
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{
"Header": {
"Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
"Info": "Performance Monitoring Events for 10th Generation Intel(R) Core(TM) Processor - V1.18",
"DatePublished": "04/25/2023",
"Version": "1.18",
"Info": "Performance Monitoring Events for 10th Generation Intel(R) Core(TM) Processor - V1.19",
"DatePublished": "06/06/2023",
"Version": "1.19",
"Legend": ""
},
"Events": [
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"EventCode": "0x24",
"UMask": "0x3f",
"EventName": "L2_RQSTS.MISS",
"BriefDescription": "All requests that miss L2 cache. This event is not supported on ICL and ICX products, only supported on RKL products.",
"PublicDescription": "Counts all requests that miss L2 cache. This event is not supported on ICL and ICX products, only supported on RKL products.",
"BriefDescription": "This event is deprecated.",
"PublicDescription": "This event is deprecated.",
"Counter": "0,1,2,3",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
Expand All @@ -700,7 +700,7 @@
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Deprecated": "1",
"Speculative": "1"
},
{
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"EventCode": "0x24",
"UMask": "0xff",
"EventName": "L2_RQSTS.REFERENCES",
"BriefDescription": "All L2 requests. This event is not supported on ICL and ICX products, only supported on RKL products.",
"PublicDescription": "Counts all L2 requests. This event is not supported on ICL and ICX products, only supported on RKL products.",
"BriefDescription": "This event is deprecated.",
"PublicDescription": "This event is deprecated.",
"Counter": "0,1,2,3",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
Expand All @@ -916,7 +916,7 @@
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Deprecated": "1",
"Speculative": "1"
},
{
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"EventCode": "0x80",
"UMask": "0x04",
"EventName": "ICACHE_16B.IFDATA_STALL",
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
"PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.",
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss. [This event is alias to ICACHE_DATA.STALLS]",
"PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity. [This event is alias to ICACHE_DATA.STALLS]",
"Counter": "0,1,2,3",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "500009",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Speculative": "1"
},
{
"EventCode": "0x80",
"UMask": "0x04",
"EventName": "ICACHE_DATA.STALLS",
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss. [This event is alias to ICACHE_16B.IFDATA_STALL]",
"PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity. [This event is alias to ICACHE_16B.IFDATA_STALL]",
"Counter": "0,1,2,3",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "500009",
Expand Down Expand Up @@ -2291,8 +2315,32 @@
"EventCode": "0x83",
"UMask": "0x04",
"EventName": "ICACHE_64B.IFTAG_STALL",
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
"PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]",
"PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]",
"Counter": "0,1,2,3",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Speculative": "1"
},
{
"EventCode": "0x83",
"UMask": "0x04",
"EventName": "ICACHE_TAG.STALLS",
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL]",
"PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL]",
"Counter": "0,1,2,3",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
Expand Down Expand Up @@ -2459,8 +2507,32 @@
"EventCode": "0x87",
"UMask": "0x01",
"EventName": "ILD_STALL.LCP",
"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
"PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.",
"BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to DECODE.LCP]",
"PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to DECODE.LCP]",
"Counter": "0,1,2,3",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "500009",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Speculative": "1"
},
{
"EventCode": "0x87",
"UMask": "0x01",
"EventName": "DECODE.LCP",
"BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to ILD_STALL.LCP]",
"PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to ILD_STALL.LCP]",
"Counter": "0,1,2,3",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "500009",
Expand Down Expand Up @@ -3036,7 +3108,7 @@
"UMask": "0x08",
"EventName": "TOPDOWN.BR_MISPREDICT_SLOTS",
"BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions",
"PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.",
"PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the speculative path as well as the out-of-order engine recovery past a branch misprediction.",
"Counter": "0,1,2,3,4,5,6,7",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "10000003",
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6 changes: 3 additions & 3 deletions ICL/events/icelake_uncore.json
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{
"Header": {
"Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
"Info": "Performance Monitoring Events for 10th Generation Intel(R) Core(TM) Processor - V1.18",
"DatePublished": "04/25/2023",
"Version": "1.18",
"Info": "Performance Monitoring Events for 10th Generation Intel(R) Core(TM) Processor - V1.19",
"DatePublished": "06/06/2023",
"Version": "1.19",
"Legend": ""
},
"Events": [
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6 changes: 3 additions & 3 deletions ICL/events/icelake_uncore_experimental.json
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{
"Header": {
"Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
"Info": "Performance Monitoring Events for 10th Generation Intel(R) Core(TM) Processor - V1.18",
"DatePublished": "04/25/2023",
"Version": "1.18",
"Info": "Performance Monitoring Events for 10th Generation Intel(R) Core(TM) Processor - V1.19",
"DatePublished": "06/06/2023",
"Version": "1.19",
"Legend": ""
},
"Events": [
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18 changes: 9 additions & 9 deletions mapfile.csv
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Expand Up @@ -97,15 +97,15 @@ GenuineIntel-6-55-[56789ABCDEF],V1.19,/CLX/events/cascadelakex_uncore_experiment
GenuineIntel-6-7A,V1.01,/GLP/events/goldmontplus_core.json,core,,,
GenuineIntel-6-7A,V1.01,/GLP/events/goldmontplus_fp_arith_inst.json,fp_arith_inst,,,
GenuineIntel-6-7A,V1.01,/GLP/events/goldmontplus_matrix.json,offcore,,,
GenuineIntel-6-7D,V1.18,/ICL/events/icelake_core.json,core,,,
GenuineIntel-6-7D,V1.18,/ICL/events/icelake_uncore.json,uncore,,,
GenuineIntel-6-7D,V1.18,/ICL/events/icelake_uncore_experimental.json,uncore experimental,,,
GenuineIntel-6-7E,V1.18,/ICL/events/icelake_core.json,core,,,
GenuineIntel-6-7E,V1.18,/ICL/events/icelake_uncore.json,uncore,,,
GenuineIntel-6-7E,V1.18,/ICL/events/icelake_uncore_experimental.json,uncore experimental,,,
GenuineIntel-6-A7,V1.18,/ICL/events/icelake_core.json,core,,,
GenuineIntel-6-A7,V1.18,/ICL/events/icelake_uncore.json,uncore,,,
GenuineIntel-6-A7,V1.18,/ICL/events/icelake_uncore_experimental.json,uncore experimental,,,
GenuineIntel-6-7D,V1.19,/ICL/events/icelake_core.json,core,,,
GenuineIntel-6-7D,V1.19,/ICL/events/icelake_uncore.json,uncore,,,
GenuineIntel-6-7D,V1.19,/ICL/events/icelake_uncore_experimental.json,uncore experimental,,,
GenuineIntel-6-7E,V1.19,/ICL/events/icelake_core.json,core,,,
GenuineIntel-6-7E,V1.19,/ICL/events/icelake_uncore.json,uncore,,,
GenuineIntel-6-7E,V1.19,/ICL/events/icelake_uncore_experimental.json,uncore experimental,,,
GenuineIntel-6-A7,V1.19,/ICL/events/icelake_core.json,core,,,
GenuineIntel-6-A7,V1.19,/ICL/events/icelake_uncore.json,uncore,,,
GenuineIntel-6-A7,V1.19,/ICL/events/icelake_uncore_experimental.json,uncore experimental,,,
GenuineIntel-6-86,V1.21,/SNR/events/snowridgex_core.json,core,,,
GenuineIntel-6-86,V1.21,/SNR/events/snowridgex_uncore.json,uncore,,,
GenuineIntel-6-86,V1.21,/SNR/events/snowridgex_uncore_experimental.json,uncore experimental,,,
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