Welcome to ROHD Discussions!

[mkorbel1]

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[mars441998]

Hello @mkorbel1 , I am Abdur-Rehman, currently working as Verification engineer in a US based startup. Currently working on verification of IEEE 802.3 (Ethernet MAC). I read about this on LinkedIn and found it interesting. I was wondering if you guys have any plan to publish this ROHD on long scale for designers and verification engineers? Do you have any plan to have some sort of webinar like thing?

Thanks and regards,
Abdur-Rehman

[mkorbel1]

Hi @mars441998 , thanks for your interest! Development is active and planned beyond what ROHD currently offers, and it is also open for open source contributions. ROHD will grow directly in this repository, but also through a growing ecosystem of packages which use ROHD. I'm happy to give a presentation if you are interested.

[mars441998]

Hi @mkorbel1 , it will be really helpful to get more insight about this through any presentation.

[mkorbel1]

Sure, we can set up a call where I can present on it. You can reach me at max.korbel@intel.com and we can set something up.

[mars441998]

Sure I will contact you.

[saw235]

Hi @mkorbel1 , a few questions:

1. How is the simulation performance compared to traditional SV simulations? Are there any papers associated with ROHD?
2. In Chisel, there were some complaints about the generated code being difficult to debug. Do you see similar issues with ROHD?

[mkorbel1]

We don't yet have any formal benchmarks comparing simulator performance, but initial experiments are showing that it performs extremely well. We think the fact that it doesn't need to parse another language (i.e. SystemVerilog) and the Dart JIT compiler are contributing factors to the impressive performance.

There are no papers published on ROHD yet, but hopefully soon!

Code generated by ROHD is intended to be structurally similar to the original implementation and maintain signal and port names. The generated code should look similar to how you would write the SystemVerilog code yourself. Other solutions can do lots of layers of optimization on the generated code to the point where it nearly looks like a netlist, which is nearly impossible to debug. Most of the primitives in ROHD map 1-to-1 to a structure in SystemVerilog, without any fancy optimization steps in between, making it easy to see how your design is represented. Also, since ROHD has a simulator built in, a lot of your testbench development and debug time will be spent in Dart/ROHD rather than on generated code on a SystemVerilog simulator. Some other solutions only generate the code, forcing you to do your testing and simulation on the generated content.

[alexporter8013]

Do you think ROHD would benefit from integration with F* or Low* to add formal verification in line with the verification frameworks you aim to provide with ROHD?

[mkorbel1]

I'm not that familiar with F* or Low*, but adding formal verification is definitely something that would be great to support with ROHD! Do you have some thoughts on ways F*/Low* and ROHD might integrate well together?

[alexporter8013]

F* was originally designed to convert to OCAML, but Low* was an extension added to allow conversion to C. My first thought would be that Low* could be extended to allow conversion to Dart/ROHD. After which, it could be integrated with the rest of ROHD. Being that I'm an expert in exactly none of these things, I could be completely wrong, but it could be worth a look.

[mkorbel1]

Interesting, thanks for sharing! I'll definitely keep it in mind as we start looking at formal for ROHD. We're also open for contributions, either directly to ROHD or as a separate independent package that depends on ROHD, if you (or anyone else) want to take a stab at starting something like this!