Generated SystemVerilog uses bit slicing on expressions, illegal in SystemVerilog

[mkorbel1]

Describe the bug

In SystemVerilog, it is not legal to use bit slicing on an expression. For example, this is invalid:

assign expression_bit_select = ({a_b_joined,a_shrunk,a_range,a_rsliced,a_plus_b})[3:0];

ROHD currently generates code like this, which is illegal.

To Reproduce

Perform a slice on an inlineable expression and then generate SystemVerilog of it.

Expected behavior

Valid SystemVerilog is generated. One solution is an intermediate signal for the expression which is then sliced.

Actual behavior

Illegal SystemVerilog is generated.

Additional details

Found as part of debug on #158