Adds atomic.fence to core spec.

Addreses issue WebAssembly#188

document/core/binary/instructions.rst

@@ -185,6 +185,7 @@ Atomic Memory Instructions
 
 Each variant of :ref:`atomic memory instruction <syntax-instr-atomic-memory>` is encoded with a different byte code. Loads, stores and RMW instructions are followed by the encoding of their |memarg| immediate.
 
+.. _binary-atomic-fence:
 .. _binary-atomic-wait:
 .. _binary-atomic-notify:
 .. _binary-atomic-load:
@@ -200,6 +201,7 @@ Each variant of :ref:`atomic memory instruction <syntax-instr-atomic-memory>` is
      \hex{FE}~\hex{00}~~m{:}\Bmemarg &\Rightarrow& \MEMORYATOMICNOTIFY~m \\ &&|&
      \hex{FE}~\hex{01}~~m{:}\Bmemarg &\Rightarrow& \MEMORYATOMICWAIT\K{32}~m \\ &&|&
      \hex{FE}~\hex{02}~~m{:}\Bmemarg &\Rightarrow& \MEMORYATOMICWAIT\K{64}~m \\
+     \hex{FE}~\hex{03}~\hex{00} &\Rightarrow& \MEMORYATOMICFENCE \\
    \end{array}
 
 

document/core/exec/instructions.rst

@@ -1195,6 +1195,13 @@ The rules are identical to :ref:`non-atomic stores <exec-store>`, except that :m
    \end{array}
    \end{array}
 
+.. _exec-memory.atomic.fence:
+
+:math:`\MEMORYATOMICFENCE`
+..........................
+
+.. todo::
+   Add semantics for fence.
 
 .. index:: control instructions, structured control, label, block, branch, result type, label index, function index, type index, vector, address, table address, table instance, store, frame
    pair: execution; instruction

document/core/syntax/instructions.rst

@@ -308,7 +308,8 @@ Instructions in this group are concerned with accessing :ref:`linear memory <syn
      \K{i}\X{nn}\K{.}\ATOMICRMW\K{16.}\ATCMPXCHG\K{\_u}~\memarg \\&&|&
      \K{i64.}\ATOMICRMW\K{32.}\ATCMPXCHG\K{\_u}~\memarg \\&&|&
      \MEMORYATOMICNOTIFY~\memarg \\&&|&
-     \MEMORYATOMICWAIT\X{nn}~\memarg \\
+     \MEMORYATOMICWAIT\X{nn}~\memarg \\&&|&
+     \MEMORYATOMICFENCE \\
    \end{array}
 
 Memory is accessed atomically using the |ATOMICLOAD|, |ATOMICSTORE|, and
@@ -325,12 +326,13 @@ The |ATCMPXCHG| operator is similar, but only performs this action conditionally
 if the read value is equal to a provided comparison argument.
 All other atomic operators have the same behavior as the :ref:`binary operator <syntax-ibinop>` of the same name.
 
-The |MEMORYATOMICWAIT| and |MEMORYATOMICNOTIFY| instructions provide primitive
+The |MEMORYATOMICWAIT|, |MEMORYATOMICNOTIFY|, and |MEMORYATOMICFENCE| instructions provide primitive
 synchronization between :ref:`threads <syntax-thread>`.
 The |MEMORYATOMICWAIT| instructions atomically load a value from the calculated effective address and compare it to an expected value.
 If they are equal, the thread is then suspended until a given timeout expires or another thread wakes it.
 The |MEMORYATOMICNOTIFY| instruction wakes threads that are waiting on a given
 address, up to a given maximum.
+The |MEMORYATOMICFENCE| instruction takes no operands, and returns nothing. It is intended to preserve the synchronization guarantees of the fence operators of higher-level languages. Unlike other atomic operators, it does not target a particular linear memory.
 
 
 .. index:: ! control instruction, ! structured control, ! label, ! block, ! block type, ! branch, ! unwinding, result type, label index, function index, type index, vector, trap, function, table, function type, value type, type index

document/core/text/instructions.rst

@@ -241,6 +241,7 @@ Lexically, an |Toffset| or |Talign| phrase is considered a single :ref:`keyword
 Atomic Memory Instructions
 ~~~~~~~~~~~~~~~~~~~~~~~~~~
 
+.. _text-atomic-fence:
 .. _text-atomic-wait:
 .. _text-atomic-notify:
 .. _text-atomic-load:
@@ -258,7 +259,8 @@ The offset immediate to atomic memory instructions is optional, and defaults to
    \production{instruction} & \Tplaininstr_I &::=& \dots \phantom{thisshouldbeenoughnowitissee} && \phantom{thisshouldbeenough} \\ &&|&
      \text{memory.atomic.notify}~~m{:}\Tmemarg_4 &\Rightarrow& \MEMORYATOMICNOTIFY~m \\ &&|&
      \text{memory.atomic.wait32}~~m{:}\Tmemarg_4 &\Rightarrow& \MEMORYATOMICWAIT\K{32}~m \\ &&|&
-     \text{memory.atomic.wait64}~~m{:}\Tmemarg_8 &\Rightarrow& \MEMORYATOMICWAIT\K{64}~m \\
+     \text{memory.atomic.wait64}~~m{:}\Tmemarg_8 &\Rightarrow& \MEMORYATOMICWAIT\K{64}~m \\ &&|&
+     \text{memory.atomic.fence} &\Rightarrow& \MEMORYATOMICFENCE \\
    \end{array}
 
 .. math::

document/core/util/macros.def

@@ -395,6 +395,7 @@
 .. |ATOMICRMW| mathdef:: \xref{syntax/instructions}{syntax-instr-atomic-memory}{\K{atomic.rmw}}
 .. |MEMORYATOMICWAIT| mathdef:: \xref{syntax/instructions}{syntax-instr-atomic-memory}{\K{memory.atomic.wait}}
 .. |MEMORYATOMICNOTIFY| mathdef:: \xref{syntax/instructions}{syntax-instr-atomic-memory}{\K{memory.atomic.notify}}
+.. |MEMORYATOMICFENCE| mathdef:: \xref{syntax/instructions}{syntax-instr-atomic-memory}{\K{memory.atomic.fence}}
 
 
 .. Instructions, non-terminals

document/core/valid/instructions.rst

@@ -639,6 +639,21 @@ Atomic Memory Instructions
      C \vdash \MEMORYATOMICWAIT{N}~\memarg : [\I32~\K{i}{N}~\I64] \to [\I32]
    }
 
+.. _valid-memory.atomic.fence:
+
+:math:`\MEMORYATOMICFENCE`
+..........................
+
+* The instruction is valid with type :math:`[] \to []`.
+
+.. math::
+   \frac{
+   }{
+     C \vdashinstr \MEMORYATOMICFENCE : [] \to []
+   }
+
+.. note::
+   The |MEMORYATOMICFENCE| instruction may occur in modules which declare no memory without causing a validation error.
 
 .. index:: control instructions, structured control, label, block, branch, block type, result type, label index, function index, type index, vector, polymorphism, context
    pair: validation; instruction