FPGA-VHDL

FIR Filter / pipelined / parallel processs

Implementation of an 8-bit FIR filter on zybo board in VHDL in two versions. a) Pipelined FIR filter b) Pipelined and parallel processing FIR filter

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
README.md		README.md
adder_seq.vhd		adder_seq.vhd
and_gate.vhd		and_gate.vhd
aux_unit.vhd		aux_unit.vhd
dff.vhd		dff.vhd
mul_seq.vhd		mul_seq.vhd
parallel_process.vhd		parallel_process.vhd
parallel_process_tb.vhd		parallel_process_tb.vhd
pipeline_fir.vhd		pipeline_fir.vhd
pipeline_fir_tb.vhd		pipeline_fir_tb.vhd

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