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Add test coverage for ipbus ram slaves #81

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alessandrothea opened this issue Dec 5, 2018 · 1 comment
Closed

Add test coverage for ipbus ram slaves #81

alessandrothea opened this issue Dec 5, 2018 · 1 comment
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@alessandrothea
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enhancement task
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Release 1.3

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@alessandrothea
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The existing automatic tests don't provide appropriate coverage of the ipbus ram slave code.
Dedicated tests have to be added, covering

  • VHDL Syntax
  • Interface with ipbus
  • interface with the payload clock logic

The latter will require adding a dedicated pattern generator.
alessandrothea added a commit that referenced this issue Dec 5, 2018
@alessandrothea
Adding ipbus_extended_slaves entity. See #81
b53b530
alessandrothea added a commit that referenced this issue Dec 5, 2018
@alessandrothea
Working on extended examples. See #81
61ff773
alessandrothea added a commit that referenced this issue Dec 5, 2018
@alessandrothea
Bugfix in dpram - wrong datawidth in an assignment statement. See #81
3bc69a7 
Working on the test script.
alessandrothea added a commit that referenced this issue Dec 5, 2018
@alessandrothea
Added a pattern-generator for testing dual-port rams interface with n…
fdb279f 
…on-ipbus clock domains. See #81
alessandrothea added a commit that referenced this issue Dec 5, 2018
@alessandrothea
Fixed sim path in sim test job. See #81
b45c013
alessandrothea added a commit that referenced this issue Dec 5, 2018
@alessandrothea
Fixed sim path in test_build.sh. See #81
25d42a9
alessandrothea added a commit that referenced this issue Dec 5, 2018
@alessandrothea
Improved pattern generator word-based pattern implementation. See #81
0590726
alessandrothea added a commit that referenced this issue Dec 5, 2018
@alessandrothea
dpram36 failed to syntesize - fixed. See #81
d1f0566 
Vivado couldn't infer the ram correctly. Made the signal layout closer to
ported_dram36 (which worked) and made Vivado happy again.
enclustra top-level updated.
alessandrothea added a commit that referenced this issue Dec 5, 2018
@alessandrothea
Tweaks to the test script. See #81
c99983e
alessandrothea added a commit that referenced this issue Dec 5, 2018
@alessandrothea
Including (and fixing) 72-bits simple port ram slaves. See #81
0a0a8d9
alessandrothea added a commit that referenced this issue Dec 5, 2018
@alessandrothea
Boosting synthesis speed. See #81
cf9d666
alessandrothea added a commit that referenced this issue Dec 5, 2018
@alessandrothea
CI bugfix: execute github_commit_status:end:failure on pull request…
32cd371 
…s only. See #81
alessandrothea added a commit that referenced this issue Dec 5, 2018
@alessandrothea
Full build enabled for web pipelines. See #81
00d644b
alessandrothea added a commit that referenced this issue Dec 5, 2018
@alessandrothea
Adding missing signals to kcu105. kc705 top levels. See #81
ec069c8
alessandrothea added a commit that referenced this issue Dec 5, 2018
@alessandrothea
Fixed typo in test_sim script. See #81
c036c75
alessandrothea added a commit that referenced this issue Dec 5, 2018
@alessandrothea
slaves entity renamed payload. See #81
829a2a6
alessandrothea added a commit that referenced this issue Dec 5, 2018
@alessandrothea
Fixed simple-dual port ram72 inference. Now inferred as block rams. See
f3e3042 
#81
alessandrothea added a commit that referenced this issue Dec 5, 2018
@alessandrothea
Fixed ported spdram72 alignment with ipbus clock. See #81
d4279c7
alessandrothea added a commit that referenced this issue Dec 5, 2018
@alessandrothea
Extended examples re-organised as test project. See #81
73d79f5
alessandrothea added a commit that referenced this issue Dec 5, 2018
@alessandrothea
extended examples renamed ram_tests. See #81
66bed8a
alessandrothea added a commit that referenced this issue Dec 5, 2018
@alessandrothea
Cleanup. See #81
302ad9e
alessandrothea added a commit that referenced this issue Dec 5, 2018
@alessandrothea
Fixed ipbus_example entity name in payload. See #81
d9ef155
alessandrothea added a commit that referenced this issue Dec 5, 2018
@alessandrothea
Fixed payload example port list. See #81
ef0e4d5
alessandrothea added a commit that referenced this issue Dec 5, 2018
@alessandrothea
Updated ci jobs tools. See #81
4cdf68d 
Vivado -> 2018.2 and 2017.4
Modelsim -> 10.6c
alessandrothea added a commit that referenced this issue Dec 5, 2018
@alessandrothea
Sim job switched to Vivado 2018.2. See #81
22f317c
@alessandrothea alessandrothea mentioned this issue Dec 5, 2018
Merged
alessandrothea added a commit that referenced this issue Dec 5, 2018
@alessandrothea
Bugfix: gitlab ci . See #81
a89842f
alessandrothea added a commit that referenced this issue Dec 6, 2018
@alessandrothea
Adding ipbus_extended_slaves entity. See #81
f6469f8
alessandrothea added a commit that referenced this issue Dec 6, 2018
@alessandrothea
Working on extended examples. See #81
670f94c
alessandrothea added a commit that referenced this issue Dec 6, 2018
@alessandrothea
Bugfix in dpram - wrong datawidth in an assignment statement. See #81
44b3b7f 
Working on the test script.
alessandrothea added a commit that referenced this issue Dec 6, 2018
@alessandrothea
Improved pattern generator word-based pattern implementation. See #81
c0b0886
alessandrothea added a commit that referenced this issue Dec 6, 2018
@alessandrothea
dpram36 failed to syntesize - fixed. See #81
d4a33d7 
Vivado couldn't infer the ram correctly. Made the signal layout closer to
ported_dram36 (which worked) and made Vivado happy again.
enclustra top-level updated.
alessandrothea added a commit that referenced this issue Dec 6, 2018
@alessandrothea
Tweaks to the test script. See #81
98dc4e2
alessandrothea added a commit that referenced this issue Dec 6, 2018
@alessandrothea
Including (and fixing) 72-bits simple port ram slaves. See #81
e7ace4b
alessandrothea added a commit that referenced this issue Dec 6, 2018
@alessandrothea
Boosting synthesis speed. See #81
ed22a4c
alessandrothea added a commit that referenced this issue Dec 6, 2018
@alessandrothea
CI bugfix: execute github_commit_status:end:failure on pull request…
f25db2b 
…s only. See #81
alessandrothea added a commit that referenced this issue Dec 6, 2018
@alessandrothea
Full build enabled for web pipelines. See #81
5b1bbbd
alessandrothea added a commit that referenced this issue Dec 6, 2018
@alessandrothea
Adding missing signals to kcu105. kc705 top levels. See #81
e943749
alessandrothea added a commit that referenced this issue Dec 6, 2018
@alessandrothea
Fixed typo in test_sim script. See #81
55c3b75
alessandrothea added a commit that referenced this issue Dec 6, 2018
@alessandrothea
slaves entity renamed payload. See #81
e9c86a5
alessandrothea added a commit that referenced this issue Dec 6, 2018
@alessandrothea
Fixed simple-dual port ram72 inference. Now inferred as block rams. See
56699ed 
#81
alessandrothea added a commit that referenced this issue Dec 6, 2018
@alessandrothea
Fixed ported spdram72 alignment with ipbus clock. See #81
a6e0e86
alessandrothea added a commit that referenced this issue Dec 6, 2018
@alessandrothea
Extended examples re-organised as test project. See #81
5c67ead
alessandrothea added a commit that referenced this issue Dec 6, 2018
@alessandrothea
extended examples renamed ram_tests. See #81
e50e036
alessandrothea added a commit that referenced this issue Dec 6, 2018
@alessandrothea
Cleanup. See #81
0db7349
alessandrothea added a commit that referenced this issue Dec 6, 2018
@alessandrothea
Fixed ipbus_example entity name in payload. See #81
4e529ef
alessandrothea added a commit that referenced this issue Dec 6, 2018
@alessandrothea
Fixed payload example port list. See #81
00f04eb
alessandrothea added a commit that referenced this issue Dec 6, 2018
@alessandrothea
Updated ci jobs tools. See #81
f3b320a 
Vivado -> 2018.2 and 2017.4
Modelsim -> 10.6c
alessandrothea added a commit that referenced this issue Dec 6, 2018
@alessandrothea
Sim job switched to Vivado 2018.2. See #81
31f8c80
alessandrothea added a commit that referenced this issue Dec 6, 2018
@alessandrothea
Adding rams_tb to ci tests. See #81
0b0147d
alessandrothea added a commit that referenced this issue Dec 6, 2018
@alessandrothea
Ci tests: fixed rams_tb toolset. See #81
19972e2
alessandrothea added a commit that referenced this issue Dec 6, 2018
@alessandrothea
Bugfix: gitlab ci . See #81
f9164b5
alessandrothea added a commit that referenced this issue Dec 6, 2018
@alessandrothea
Cosmetics. See #81
014bd4d
@tswilliams tswilliams added this to the Release 1.3 milestone Dec 6, 2018
@alessandrothea
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alessandrothea commented Dec 6, 2018 •
edited

Note: Both dpram36 and spdpram72 were found to be inferred as distributed RAMs while expected to be implemented as block rams. The code has been slightly re-arranged according to the Xilinx prescriptions. They are both inferred as block RAMs, now.

alessandrothea added a commit that referenced this issue Dec 6, 2018
@alessandrothea
Ram slaves testbench name made more explicit. See #81
d5cba81
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