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missing checks in gen_ipbus_addr_decode script #193

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mkrivda opened this issue Apr 30, 2020 · 15 comments · Fixed by #195
Closed

missing checks in gen_ipbus_addr_decode script #193

mkrivda opened this issue Apr 30, 2020 · 15 comments · Fixed by #195

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@mkrivda
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mkrivda commented Apr 30, 2020

Hello.

We had 2 issues with inconsistency inside XML file, but gen_ipbus_addr_decode script has returned 0 (success) in both cases. We have found report only in \tmp folder.
I suggest to return 1 if XML file has such errors.

A) Two registers inside one slave had the same address, so there is missing address overlap check.
Here is the example:

<node id="ctpemu" address="0x120" description="ctp emulator" fwinfo="endpoint;width=5">
  <node id=  "SOC_tf_rate" address = "0xf" description = "Cal Trigger rate, TF downscaled[15:0]" />
  <node id=  "EOC_tf_rate" address = "0xf" description = "Cal Trigger rate, TF downscaled[15:0]" />

We have found report only in /tmp folder file OverlapReport-home-trigger-WORK-vhd-ltu_logic.xml:
Overlap report for "/home/trigger/WORK/vhd/ltu_logic.xml".
Branch 'ctpemu.SOC_tf_rate' has address 0x0000012f and mask 0xffffffff which overlaps with branch 'ctpemu.EOC_tf_rate' which has address 0x0000012f and mask 0xffffffff.

B) Endpoint width was different as block size, so there is missing check for block size in respect to endpoint width.
Here is the example:

  1. unspotted error when the last node in an .xml file:
   <node id="ttcitcnts" address="0x2600" description="Counters for outgoing signals" fwinfo="endpoint;width=6">
     <node id="TTCitcnts" address="0x0" mode="block" size="0x440" 
description="48 TTCit counters" />
   </node>

i.e. for a 'width=6' max. size is 0x40, 'size=0x440' should be reported as an error.

  1. The error is spotted only, when it causes an overlap, i.e. not last one in an .xml file:
   <node id="ttcitcnts" address="0x2600" description="Counters for outgoing signals" fwinfo="endpoint;width=6">
     <node id="TTCitcnts" address="0x0" mode="block" size="0x440" 
description="48 TTCit counters" />
   </node>
   <node id="ttcitcntsX" address="0x2700" description="Counters for outgoing signals" fwinfo="endpoint;width=6">
     <node id="TTCitcntsX" address="0x0" mode="block" size="0x40" 
description="48 TTCit counters" />
   </node>

Now we see at least warning in stdout of gen_ipbus_addr_decode (ret. code is still 0), and corresponding report in /tmp:
WARNING - Address overlaps observed - report file written at "/tmp/trigger/uhal/OverlapReport-home-trigger-WORK-vhd-ttcit_logic.xml

Overlap report for "/home/trigger/WORK/vhd/ttcit_logic.xml".
Branch 'ttcitcntsX.TTCitcntsX' has address range [0x00002700 - 0x0000273f] which overlaps with branch 'ttcitcnts.TTCitcnts' which has address range [0x00002600 - 0x00002a3f].

@dmnewbold
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Hi. Both these issues have been addressed by some improvements in the script, which is now on a feature branch for testing. Could you maybe check out the updated script, try it on your design, and make sure it fixes the two issues you mention?

alessandrothea added a commit that referenced this issue May 7, 2020
Simplified logging config.
See #193
alessandrothea added a commit that referenced this issue May 7, 2020
@juskoa
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juskoa commented May 7, 2020

With a new version of the script gen_ipbus_addr_decode (from branch feature/193-addr-table-checks) I get following error:

ERROR : Endpoint node <> has a mixture of endpoint and non-endpoint descendants
ERROR : Node errors detected, exiting early before writing output

The same .xml file is processed without error with a script from master branch.
There is an endpoint keyword in each direct descendant of the TOP node.
Do we have to declare endpoint with all, i.e. also not direct descendants of the TOP node?
Here is an .xml:
ttcit_logicxml.txt

@dmnewbold
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Hi - if I run the script on that file, I don't see any error? The endpoint flag should be used to signify a block that has a concrete implementation in firmware as an ipbus slave or an address decoder. That means that you cannot mix 'physical' descendant nodes with 'logical' ones...

@dmnewbold
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This is my output:

-bash-4.2$ ./gen_ipbus_addr_decode -v test.xml
07-05-20 16:35:11.382983 [7f89849e5740] DEBUG - Parsed "file://test.xml" to:
07-05-20 16:35:11.383023 [7f89849e5740] DEBUG - > [file] "test.xml"
07-05-20 16:35:11.383057 [7f89849e5740] DEBUG - lPath was "test.xml"
07-05-20 16:35:11.383066 [7f89849e5740] DEBUG - aParentPath is "/net/home/ppd/dmn/gen"
07-05-20 16:35:11.383078 [7f89849e5740] DEBUG - lPath now "/net/home/ppd/dmn/gen/test.xml"
07-05-20 16:35:11.383102 [7f89849e5740] DEBUG - Shell expansion of "test.xml" returned:
07-05-20 16:35:11.383115 [7f89849e5740] DEBUG - > [file] /net/home/ppd/dmn/gen/test.xml
07-05-20 16:35:11.383219 [7f89849e5740] INFO - Reading XML address file "/net/home/ppd/dmn/gen/test.xml"
07-05-20 16:35:11.383333 [7f89849e5740] DEBUG - boardid built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383350 [7f89849e5740] DEBUG - fwinfo built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383376 [7f89849e5740] DEBUG - status built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383387 [7f89849e5740] DEBUG - fpga_temperature built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383398 [7f89849e5740] DEBUG - fpga_vccaux built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383415 [7f89849e5740] DEBUG - fpga_vccint built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383426 [7f89849e5740] DEBUG - fpga_vccbram built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383437 [7f89849e5740] DEBUG - fpga_alarms built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383449 [7f89849e5740] DEBUG - ctrl built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383459 [7f89849e5740] DEBUG - scopea built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383469 [7f89849e5740] DEBUG - scopeb built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383482 [7f89849e5740] DEBUG - fmcsfpsel built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383492 [7f89849e5740] DEBUG - ledenable built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383502 [7f89849e5740] DEBUG - sfpledenable built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383514 [7f89849e5740] DEBUG - adc_test_data built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383524 [7f89849e5740] DEBUG - c_spare2 built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383538 [7f89849e5740] DEBUG - ctrl built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383555 [7f89849e5740] DEBUG - iprog_icap built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383580 [7f89849e5740] DEBUG - icap_status built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383601 [7f89849e5740] DEBUG - icap built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383616 [7f89849e5740] DEBUG - ram built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383630 [7f89849e5740] DEBUG - reg built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383646 [7f89849e5740] DEBUG - addr built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383660 [7f89849e5740] DEBUG - data built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383670 [7f89849e5740] DEBUG - pram built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383688 [7f89849e5740] DEBUG - userregs built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383699 [7f89849e5740] DEBUG - i2cmain built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383715 [7f89849e5740] DEBUG - cfg built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383726 [7f89849e5740] DEBUG - errorcount built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383737 [7f89849e5740] DEBUG - startcount built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383746 [7f89849e5740] DEBUG - bbert built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383767 [7f89849e5740] DEBUG - rs built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383778 [7f89849e5740] DEBUG - spiadc built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383796 [7f89849e5740] DEBUG - userregs built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383805 [7f89849e5740] DEBUG - i2cpll built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383822 [7f89849e5740] DEBUG - ctrl built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383836 [7f89849e5740] DEBUG - data built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383846 [7f89849e5740] DEBUG - ssm built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383863 [7f89849e5740] DEBUG - ssm_control built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383876 [7f89849e5740] DEBUG - ssm_status built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383887 [7f89849e5740] DEBUG - ssm_address built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383898 [7f89849e5740] DEBUG - ssm_r_address built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383908 [7f89849e5740] DEBUG - ssmctrl built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383925 [7f89849e5740] DEBUG - ctrl built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383940 [7f89849e5740] DEBUG - data built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383950 [7f89849e5740] DEBUG - tdg built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383965 [7f89849e5740] DEBUG - ssm_control built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383978 [7f89849e5740] DEBUG - ssm_status built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.383988 [7f89849e5740] DEBUG - ssm_address built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384000 [7f89849e5740] DEBUG - ssm_r_address built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384008 [7f89849e5740] DEBUG - tdgctrl built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384025 [7f89849e5740] DEBUG - Select built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384037 [7f89849e5740] DEBUG - Num_Words built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384049 [7f89849e5740] DEBUG - Do_it built by uhal::Node* uhal::NodeTreeBuilder::bitmaskNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384057 [7f89849e5740] DEBUG - Command built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384072 [7f89849e5740] DEBUG - Busy built by uhal::Node* uhal::NodeTreeBuilder::bitmaskNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384082 [7f89849e5740] DEBUG - Status built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384095 [7f89849e5740] DEBUG - Key built by uhal::Node* uhal::NodeTreeBuilder::bitmaskNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384107 [7f89849e5740] DEBUG - Lock built by uhal::Node* uhal::NodeTreeBuilder::bitmaskNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384117 [7f89849e5740] DEBUG - Terr built by uhal::Node* uhal::NodeTreeBuilder::bitmaskNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384127 [7f89849e5740] DEBUG - Key_Lock built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384138 [7f89849e5740] DEBUG - Timeout built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384151 [7f89849e5740] DEBUG - Outgoing built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384163 [7f89849e5740] DEBUG - Incoming built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384172 [7f89849e5740] DEBUG - FLASH_SPI_Ram_0 built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384187 [7f89849e5740] DEBUG - Select built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384200 [7f89849e5740] DEBUG - Num_Words built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384213 [7f89849e5740] DEBUG - Do_it built by uhal::Node* uhal::NodeTreeBuilder::bitmaskNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384222 [7f89849e5740] DEBUG - Command built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384234 [7f89849e5740] DEBUG - Busy built by uhal::Node* uhal::NodeTreeBuilder::bitmaskNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384242 [7f89849e5740] DEBUG - Status built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384256 [7f89849e5740] DEBUG - Key built by uhal::Node* uhal::NodeTreeBuilder::bitmaskNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384268 [7f89849e5740] DEBUG - Lock built by uhal::Node* uhal::NodeTreeBuilder::bitmaskNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384278 [7f89849e5740] DEBUG - Terr built by uhal::Node* uhal::NodeTreeBuilder::bitmaskNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384287 [7f89849e5740] DEBUG - Key_Lock built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384298 [7f89849e5740] DEBUG - Timeout built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384311 [7f89849e5740] DEBUG - Outgoing built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384323 [7f89849e5740] DEBUG - Incoming built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384333 [7f89849e5740] DEBUG - FLASH_SPI_Ram_1 built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384350 [7f89849e5740] DEBUG - TTCitcnts built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384361 [7f89849e5740] DEBUG - ttcitcnts built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384378 [7f89849e5740] DEBUG - TTCitcnts_channelA_BCRST built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384389 [7f89849e5740] DEBUG - ttcitcnts_channelA_BCRST built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384401 [7f89849e5740] DEBUG - TOP built by uhal::Node* uhal::NodeTreeBuilder::plainNodeCreator(const bool&, const pugi::xml_node&)
07-05-20 16:35:11.384498 [7f89849e5740] INFO - ConnectionManager created node tree:

  • Node "TOP", Address 0x00000000, Module "/net/home/ppd/dmn/gen/test.xml"
    • Node "ctrl", Address 0x00000000, Description "stat ctrl regs", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "boardid", SINGLE register, Address 0x00000000, Mask 0xFFFFFFFF, Permissions r-, Description "7-0: xx in MAC:08-00-30-00-2A-xx", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "fwinfo", SINGLE register, Address 0x00000001, Mask 0xFFFFFFFF, Permissions r-, Description "31-24:type 23-8:version 7-0:subversion", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "status", SINGLE register, Address 0x00000002, Mask 0xFFFFFFFF, Permissions r-, Description "1:SI5345_INTR 0:SI5345_LOL", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "fpga_temperature", SINGLE register, Address 0x00000003, Mask 0xFFFFFFFF, Permissions r-, Description "bits 15..0", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "fpga_vccaux", SINGLE register, Address 0x00000004, Mask 0xFFFFFFFF, Permissions r-, Description "bits 15..0", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "fpga_vccint", SINGLE register, Address 0x00000005, Mask 0xFFFFFFFF, Permissions r-, Description "bits 15..0", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "fpga_vccbram", SINGLE register, Address 0x00000006, Mask 0xFFFFFFFF, Permissions r-, Description "bits 15..0", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "fpga_alarms", SINGLE register, Address 0x00000007, Mask 0xFFFFFFFF, Permissions r-, Description "bits 15..0", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "ctrl", SINGLE register, Address 0x00000008, Mask 0xFFFFFFFF, Permissions rw, Description "1:soft ipbus reset,0:ipbus reset", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "scopea", SINGLE register, Address 0x00000009, Mask 0xFFFFFFFF, Permissions rw, Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "scopeb", SINGLE register, Address 0x0000000A, Mask 0xFFFFFFFF, Permissions rw, Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "fmcsfpsel", SINGLE register, Address 0x0000000B, Mask 0xFFFFFFFF, Permissions rw, Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "ledenable", SINGLE register, Address 0x0000000C, Mask 0xFFFFFFFF, Permissions rw, Description "24..0", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "sfpledenable", SINGLE register, Address 0x0000000D, Mask 0xFFFFFFFF, Permissions rw, Description "23..0", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "adc_test_data", SINGLE register, Address 0x0000000E, Mask 0xFFFFFFFF, Permissions rw, Description "31..0", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "c_spare2", SINGLE register, Address 0x0000000F, Mask 0xFFFFFFFF, Permissions rw, Module "/net/home/ppd/dmn/gen/test.xml"
    • Node "icap", Address 0x00000100, Description "N_SLV_ICAP", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "iprog_icap", SINGLE register, Address 0x00000100, Mask 0xFFFFFFFF, Permissions -w, Description "data", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "icap_status", SINGLE register, Address 0x00000101, Mask 0xFFFFFFFF, Permissions r-, Description "avail[31],prdone[30],prerror[29]", Module "/net/home/ppd/dmn/gen/test.xml"
    • Node "ram", INCREMENTAL block, Size 1024, Addresses [0x00001000-000013FF], Permissions rw, Description "1kword RAM", Module "/net/home/ppd/dmn/gen/test.xml"
    • Node "reg", SINGLE register, Address 0x00001400, Mask 0xFFFFFFFF, Permissions rw, Description "read-write register", Module "/net/home/ppd/dmn/gen/test.xml"
    • Node "pram", Address 0x00002000, Description "1kword peephole RAM", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "addr", SINGLE register, Address 0x00002000, Mask 0xFFFFFFFF, Permissions rw, Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "data", NON-INCREMENTAL block, Size 1024, Address 0x00002001, Permissions rw, Module "/net/home/ppd/dmn/gen/test.xml"
    • Node "i2cmain", Address 0x00002008, Description "I2C master controller", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "userregs", INCREMENTAL block, Size 8, Addresses [0x00002008-0000200F], Permissions rw, Description "regs:pslo,pshi,ctrl,data,cmd_stat", Module "/net/home/ppd/dmn/gen/test.xml"
    • Node "bbert", Address 0x00002020, Description "BBERT", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "cfg", SINGLE register, Address 0x00002020, Mask 0xFFFFFFFF, Permissions rw, Description "7-0:inpNumber 15-8:outNumber 19-16:signal delay 20:resetTransmitter 21: resetReceiver 22:resetPLL", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "errorcount", SINGLE register, Address 0x00002021, Mask 0xFFFFFFFF, Permissions rw, Description "errorCount", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "startcount", SINGLE register, Address 0x00002022, Mask 0xFFFFFFFF, Permissions rw, Description "startCount", Module "/net/home/ppd/dmn/gen/test.xml"
    • Node "spiadc", Address 0x00002028, Description "SPI master controller: ADC", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "rs", INCREMENTAL block, Size 8, Addresses [0x00002028-0000202F], Permissions rw, Description "regs:d0-d4,ctrl,divider,ss", Module "/net/home/ppd/dmn/gen/test.xml"
    • Node "i2cpll", Address 0x00002030, Description "I2C for si5345 lhc clock", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "userregs", INCREMENTAL block, Size 8, Addresses [0x00002030-00002037], Permissions rw, Description "regs:pslo,pshi,ctrl,data,cmd_stat", Module "/net/home/ppd/dmn/gen/test.xml"
    • Node "ssm", Address 0x00002040, Description "DDR4 Snapshot Memory", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "ctrl", INCREMENTAL block, Size 8, Addresses [0x00002040-00002047], Permissions rw, Description "5 control/status regs for r/w access to ddr4", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "data", NON-INCREMENTAL block, Size 1048576, Address 0x00002048, Permissions rw, Description "data", Module "/net/home/ppd/dmn/gen/test.xml"
    • Node "ssmctrl", Address 0x00002050, Description "Control of SSM for R/W from/to ONU clock domain", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "ssm_control", SINGLE register, Address 0x00002050, Mask 0xFFFFFFFF, Permissions rw, Description "Reset_BC[8], SSM_TxRxData_sel[4], SSM_mode[2], SSM_stop[1], SSM_start[0]", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "ssm_status", SINGLE register, Address 0x00002054, Mask 0xFFFFFFFF, Permissions rw, Description "SSM_r_overflow[3], SSM overflow[2], SSM_r_busy[1], SSM_busy[0]", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "ssm_address", SINGLE register, Address 0x00002055, Mask 0xFFFFFFFF, Permissions rw, Description "SSM_add[28:0]", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "ssm_r_address", SINGLE register, Address 0x00002056, Mask 0xFFFFFFFF, Permissions rw, Description "SSM_r_add[28:0]", Module "/net/home/ppd/dmn/gen/test.xml"
    • Node "tdg", Address 0x00002060, Description "DDR4 Trigger Data Generator", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "ctrl", INCREMENTAL block, Size 8, Addresses [0x00002060-00002067], Permissions rw, Description "5 control/status regs for r/w access to ddr4", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "data", NON-INCREMENTAL block, Size 1048576, Address 0x00002068, Permissions rw, Description "data", Module "/net/home/ppd/dmn/gen/test.xml"
    • Node "tdgctrl", Address 0x00002070, Description "Control of TDG for R/W from/to OLT clock domain", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "ssm_control", SINGLE register, Address 0x00002070, Mask 0xFFFFFFFF, Permissions rw, Description "Reset_BC[8], TDG_TxRxData_sel[4], TDG_mode[2], TDG_stop[1], TDG_start[0]", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "ssm_status", SINGLE register, Address 0x00002074, Mask 0xFFFFFFFF, Permissions rw, Description "TDG_r_overflow[3], TDG_overflow[2], TDG_r_busy[1], TDG_busy[0]", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "ssm_address", SINGLE register, Address 0x00002075, Mask 0xFFFFFFFF, Permissions rw, Description "TDG_w_add[28:0]", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "ssm_r_address", SINGLE register, Address 0x00002076, Mask 0xFFFFFFFF, Permissions rw, Description "TDG_r_add[28:0]", Module "/net/home/ppd/dmn/gen/test.xml"
    • Node "FLASH_SPI_Ram_0", Address 0x00002200, Tags "slave", Description "SPI_RAM_0", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "Select", SINGLE register, Address 0x00002200, Mask 0xFFFFFFFF, Permissions rw, Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "Num_Words", SINGLE register, Address 0x00002202, Mask 0xFFFFFFFF, Permissions rw, Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "Command", SINGLE register, Address 0x00002203, Mask 0xFFFFFFFF, Permissions rw, Module "/net/home/ppd/dmn/gen/test.xml"
        • Node "Do_it", SINGLE register, Address 0x00002203, Mask 0x00000001, Permissions rw, Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "Status", SINGLE register, Address 0x00002204, Mask 0xFFFFFFFF, Permissions rw, Module "/net/home/ppd/dmn/gen/test.xml"
        • Node "Busy", SINGLE register, Address 0x00002204, Mask 0x00000001, Permissions rw, Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "Key_Lock", SINGLE register, Address 0x00002280, Mask 0xFFFFFFFF, Permissions rw, Module "/net/home/ppd/dmn/gen/test.xml"
        • Node "Key", SINGLE register, Address 0x00002280, Mask 0x7FFFFFFC, Permissions rw, Module "/net/home/ppd/dmn/gen/test.xml"
        • Node "Lock", SINGLE register, Address 0x00002280, Mask 0x00000002, Permissions rw, Module "/net/home/ppd/dmn/gen/test.xml"
        • Node "Terr", SINGLE register, Address 0x00002280, Mask 0x00000001, Permissions rw, Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "Timeout", SINGLE register, Address 0x00002281, Mask 0xFFFFFFFF, Permissions rw, Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "Outgoing", INCREMENTAL block, Size 128, Addresses [0x00002300-0000237F], Permissions rw, Description "128word RAM", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "Incoming", INCREMENTAL block, Size 128, Addresses [0x00002380-000023FF], Permissions rw, Description "128word RAM", Module "/net/home/ppd/dmn/gen/test.xml"
    • Node "FLASH_SPI_Ram_1", Address 0x00002400, Tags "slave", Description "SPI_RAM_1", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "Select", SINGLE register, Address 0x00002400, Mask 0xFFFFFFFF, Permissions rw, Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "Num_Words", SINGLE register, Address 0x00002402, Mask 0xFFFFFFFF, Permissions rw, Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "Command", SINGLE register, Address 0x00002403, Mask 0xFFFFFFFF, Permissions rw, Module "/net/home/ppd/dmn/gen/test.xml"
        • Node "Do_it", SINGLE register, Address 0x00002403, Mask 0x00000001, Permissions rw, Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "Status", SINGLE register, Address 0x00002404, Mask 0xFFFFFFFF, Permissions rw, Module "/net/home/ppd/dmn/gen/test.xml"
        • Node "Busy", SINGLE register, Address 0x00002404, Mask 0x00000001, Permissions rw, Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "Key_Lock", SINGLE register, Address 0x00002480, Mask 0xFFFFFFFF, Permissions rw, Module "/net/home/ppd/dmn/gen/test.xml"
        • Node "Key", SINGLE register, Address 0x00002480, Mask 0x7FFFFFFC, Permissions rw, Module "/net/home/ppd/dmn/gen/test.xml"
        • Node "Lock", SINGLE register, Address 0x00002480, Mask 0x00000002, Permissions rw, Module "/net/home/ppd/dmn/gen/test.xml"
        • Node "Terr", SINGLE register, Address 0x00002480, Mask 0x00000001, Permissions rw, Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "Timeout", SINGLE register, Address 0x00002481, Mask 0xFFFFFFFF, Permissions rw, Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "Outgoing", INCREMENTAL block, Size 128, Addresses [0x00002500-0000257F], Permissions rw, Description "128word RAM", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "Incoming", INCREMENTAL block, Size 128, Addresses [0x00002580-000025FF], Permissions rw, Description "128word RAM", Module "/net/home/ppd/dmn/gen/test.xml"
    • Node "ttcitcnts", Address 0x00002600, Description "Counters for outgoing signals", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "TTCitcnts", INCREMENTAL block, Size 256, Addresses [0x00002600-000026FF], Permissions rw, Description "135 TTCit counters, max. is 256", Module "/net/home/ppd/dmn/gen/test.xml"
    • Node "ttcitcnts_channelA_BCRST", Address 0x00002700, Description "Counters for channel A in BCRST", Module "/net/home/ppd/dmn/gen/test.xml"
      • Node "TTCitcnts_channelA_BCRST", INCREMENTAL block, Size 16, Addresses [0x00002700-0000270F], Permissions rw, Description "16 TTCit counters in BCRST", Module "/net/home/ppd/dmn/gen/test.xml"
        07-05-20 16:35:11.385057 [7f89849e5740] INFO - URI "ipbusudp-1.3://localhost:12345" parsed as:

protocol : ipbusudp-1.3
hostname : localhost
port : 12345
path :
extension :
arguments :

DEBUG : ctrl 0x0 0x4 True
DEBUG : ctrl.boardid 0x0 None False
DEBUG : ctrl.fwinfo 0x1 None False
DEBUG : ctrl.status 0x2 None False
DEBUG : ctrl.fpga_temperature 0x3 None False
DEBUG : ctrl.fpga_vccaux 0x4 None False
DEBUG : ctrl.fpga_vccint 0x5 None False
DEBUG : ctrl.fpga_vccbram 0x6 None False
DEBUG : ctrl.fpga_alarms 0x7 None False
DEBUG : ctrl.ctrl 0x8 None False
DEBUG : ctrl.scopea 0x9 None False
DEBUG : ctrl.scopeb 0xa None False
DEBUG : ctrl.fmcsfpsel 0xb None False
DEBUG : ctrl.ledenable 0xc None False
DEBUG : ctrl.sfpledenable 0xd None False
DEBUG : ctrl.adc_test_data 0xe None False
DEBUG : ctrl.c_spare2 0xf None False
DEBUG : icap 0x100 0x1 True
DEBUG : icap.iprog_icap 0x100 None False
DEBUG : icap.icap_status 0x101 None False
DEBUG : ram 0x1000 0xa True
DEBUG : reg 0x1400 0x0 True
DEBUG : pram 0x2000 0x1 True
DEBUG : pram.addr 0x2000 None False
DEBUG : pram.data 0x2001 None False
DEBUG : i2cmain 0x2008 0x3 True
DEBUG : i2cmain.userregs 0x2008 None False
DEBUG : bbert 0x2020 0x2 True
DEBUG : bbert.cfg 0x2020 None False
DEBUG : bbert.errorcount 0x2021 None False
DEBUG : bbert.startcount 0x2022 None False
DEBUG : spiadc 0x2028 0x3 True
DEBUG : spiadc.rs 0x2028 None False
DEBUG : i2cpll 0x2030 0x3 True
DEBUG : i2cpll.userregs 0x2030 None False
DEBUG : ssm 0x2040 0x4 True
DEBUG : ssm.ctrl 0x2040 None False
DEBUG : ssm.data 0x2048 None False
DEBUG : ssmctrl 0x2050 0x3 True
DEBUG : ssmctrl.ssm_control 0x2050 None False
DEBUG : ssmctrl.ssm_status 0x2054 None False
DEBUG : ssmctrl.ssm_address 0x2055 None False
DEBUG : ssmctrl.ssm_r_address 0x2056 None False
DEBUG : tdg 0x2060 0x4 True
DEBUG : tdg.ctrl 0x2060 None False
DEBUG : tdg.data 0x2068 None False
DEBUG : tdgctrl 0x2070 0x3 True
DEBUG : tdgctrl.ssm_control 0x2070 None False
DEBUG : tdgctrl.ssm_status 0x2074 None False
DEBUG : tdgctrl.ssm_address 0x2075 None False
DEBUG : tdgctrl.ssm_r_address 0x2076 None False
DEBUG : FLASH_SPI_Ram_0 0x2200 0x9 True
DEBUG : FLASH_SPI_Ram_0.Select 0x2200 None False
DEBUG : FLASH_SPI_Ram_0.Num_Words 0x2202 None False
DEBUG : FLASH_SPI_Ram_0.Command 0x2203 None False
DEBUG : FLASH_SPI_Ram_0.Status 0x2204 None False
DEBUG : FLASH_SPI_Ram_0.Key_Lock 0x2280 None False
DEBUG : FLASH_SPI_Ram_0.Timeout 0x2281 None False
DEBUG : FLASH_SPI_Ram_0.Outgoing 0x2300 None False
DEBUG : FLASH_SPI_Ram_0.Incoming 0x2380 None False
DEBUG : FLASH_SPI_Ram_1 0x2400 0x9 True
DEBUG : FLASH_SPI_Ram_1.Select 0x2400 None False
DEBUG : FLASH_SPI_Ram_1.Num_Words 0x2402 None False
DEBUG : FLASH_SPI_Ram_1.Command 0x2403 None False
DEBUG : FLASH_SPI_Ram_1.Status 0x2404 None False
DEBUG : FLASH_SPI_Ram_1.Key_Lock 0x2480 None False
DEBUG : FLASH_SPI_Ram_1.Timeout 0x2481 None False
DEBUG : FLASH_SPI_Ram_1.Outgoing 0x2500 None False
DEBUG : FLASH_SPI_Ram_1.Incoming 0x2580 None False
DEBUG : ttcitcnts 0x2600 0x8 True
DEBUG : ttcitcnts.TTCitcnts 0x2600 None False
DEBUG : ttcitcnts_channelA_BCRST 0x2700 0x4 True
DEBUG : ttcitcnts_channelA_BCRST.TTCitcnts_channelA_BCRST 0x2700 None False
INFO : uHAL slave 0,ctrl,0b00000000000000000000000000000000,0b00000000000000000000000000001111
INFO : uHAL slave 1,icap,0b00000000000000000000000100000000,0b00000000000000000000000000000001
INFO : uHAL slave 2,ram,0b00000000000000000001000000000000,0b00000000000000000000001111111111
INFO : uHAL slave 3,reg,0b00000000000000000001010000000000,0b00000000000000000000000000000000
INFO : uHAL slave 4,pram,0b00000000000000000010000000000000,0b00000000000000000000000000000001
INFO : uHAL slave 5,i2cmain,0b00000000000000000010000000001000,0b00000000000000000000000000000111
INFO : uHAL slave 6,bbert,0b00000000000000000010000000100000,0b00000000000000000000000000000011
INFO : uHAL slave 7,spiadc,0b00000000000000000010000000101000,0b00000000000000000000000000000111
INFO : uHAL slave 8,i2cpll,0b00000000000000000010000000110000,0b00000000000000000000000000000111
INFO : uHAL slave 9,ssm,0b00000000000000000010000001000000,0b00000000000000000000000000001111
INFO : uHAL slave 10,ssmctrl,0b00000000000000000010000001010000,0b00000000000000000000000000000111
INFO : uHAL slave 11,tdg,0b00000000000000000010000001100000,0b00000000000000000000000000001111
INFO : uHAL slave 12,tdgctrl,0b00000000000000000010000001110000,0b00000000000000000000000000000111
INFO : uHAL slave 13,FLASH_SPI_Ram_0,0b00000000000000000010001000000000,0b00000000000000000000000111111111
INFO : uHAL slave 14,FLASH_SPI_Ram_1,0b00000000000000000010010000000000,0b00000000000000000000000111111111
INFO : uHAL slave 15,ttcitcnts,0b00000000000000000010011000000000,0b00000000000000000000000011111111
INFO : uHAL slave 16,ttcitcnts_channelA_BCRST,0b00000000000000000010011100000000,0b00000000000000000000000000001111
INFO : Significant address bits 0b00000000000000000011011101111000
VHDL decode file saved: ipbus_decode_test.vhd

@juskoa
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juskoa commented May 7, 2020

I just took the script alone from github and replaced it in our ipbus installation, i.e. using our uhal (cactuscore-uhal-uhal-2.6.6-1.centos7.gcc4_8_5.x86_64) in /opt/cactus/bin/uhal/tools.

Should I instead checkout branch feature/193-addr-table-checks, compile and install it in a separate directory and arrange the usage of it when starting the script?

@tswilliams
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Hi,

While I wouldn't normally recommend this, copying the script under the installed area should work in this case as all changes are contained within this script. However, if doing this you should update your installation to the latest release - version 2.7.3.

Can you retry after updating the installed software, and using the version of gen_ipbus_addr_decode from commit f796b8e14e29f4ba5b1cbc9aee8933c65841440b?

If you still see problems after doing that, can you tell us exactly what command you are running?

Thanks,
Tom

tswilliams pushed a commit that referenced this issue May 12, 2020
Simplified logging config.
See #193
tswilliams pushed a commit that referenced this issue May 12, 2020
@tswilliams
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Hi @juskoa

Did you manage to retry the script as outlined in my last comment? If not, would you have time to try it out in the next couple of days? I'm asking as in principle this branch is ready to merge, and it's passed our tests so far. Since you initially reported the bugs, it would be good to verify that the script works well for you before we merge it.

If you do have time to retry this script in the next few days, please could you use commit 9c826b4c2f47f93d0beb531c10e4c8bb305fc379?

Thanks,
Tom

@juskoa
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juskoa commented May 13, 2020 via email

@juskoa
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juskoa commented May 13, 2020

I installed uhal 2.7.3 and copied the script from feature/193-addr-table-checks.

When endpoint length < size, at the end of .xml file i.e.:

  ...
  <node id="leco1" address="0x3700" description="Link error counters for OLT_1 upstream" fwinfo="endpoint;width=6">
    <node id="data" address="0x0" mode="block" size="0x50" permission="r" description="64 Link Error counters" />
  </node>
</node>

the error is detected:

...
ERROR   : Endpoint node <<leco1>> (base address 0x3700, width 6) has a sub-node <<leco1.data>> (base address 0x3700, size 0x50) that overflows its address space
ERROR   : Node errors detected, exiting early before writing output
[trigger@acsl3 vhd]$ echo $?
2

For 'too many items' inside the node it is not detected:

...
  <node id="cdc_phase_scan" address="0x3740" fwinfo="endpoint;width=1">
    <node id="cdc_ctrl" address="0x0" /> 
    <node id="cdc_status" address="0x1" permission="r" /> 
    <node id="test" address="0x2" description="bad addr" /> 
  </node>
</node>

i.e. $? is 0 and /tmp/trigger/uhal/OverlapReport-... is not produced.

@dmnewbold
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dmnewbold commented May 13, 2020 via email

@tswilliams
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@juskoa : I tried adding the register block you mentioned to a simple test address table, but when I did this gen_ipbus_addr_decode correctly detected the problem. To make sure that we're using the same files, can you send us the full address table(s) you used when gen_ipbus_addr_decode failed to report that there were 'too many items' inside the cdc_phase_scan node?

Also, when you run this test, what's the output of running md5sum $(which gen_ipbus_addr_decode)?

@juskoa
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juskoa commented May 14, 2020

Hi Tom,
as said above, i copied it from feature/193-addr-table-checks, with '...new' name:

[root@acsl3 tools]# pwd
/opt/cactus/bin/uhal/tools
[root@acsl3 tools]# md5sum gen_ipbus_addr_decodenew 
5ac955444928391d10f3a3efaf9dd711  gen_ipbus_addr_decodenew

Here is the xml file:

<node id="TOP">
  <node id="ctrl" address="0x0" description="stat ctrl regs" fwinfo="endpoint;width=4" >
    <node id="boardid" address="0x0" permission="r" description="7-0: xx in MAC:08-00-30-00-2A-xx" />
    <node id="fwinfo" address="0x1" permission="r" description="31-24:type 23-8:version 7-0:subversion" />
    <node id="status" address="0x2" permission="r" description="1:SI5345_INTR 0:SI5345_LOL" />
    <node id="fpga_temperature" address="0x3" permission="r" description="bits 15..0" />
	<node id="fpga_vccaux" address="0x4" permission="r" description="bits 15..0" />
	<node id="fpga_vccint" address="0x5" permission="r" description="bits 15..0" />
	<node id="fpga_vccbram" address="0x6" permission="r" description="bits 15..0" />
	<node id="fpga_alarms" address="0x7" permission="r" description="bits 15..0" />
    <node id="ctrl" address="0x8" description="2:link error counters reset,1:soft ipbus reset,0:ipbus reset" />
    <node id="scopea" address="0x9" />
    <node id="scopeb" address="0xa" />
    <node id="fmcsfpsel" address="0xb" />
    <node id="ledenable" address="0xc" description="24..0"/>
    <node id="sfpledenable" address="0xd" description="23..0" />
    <node id="tdo_mux" address="0xe" description="onu_data[3],tdg_data[2],ctpemu_data_trdcpv[1],ctpemu_data[0]" /> <!-- ttcpon_data is default i.e."000"-->
    <node id="tdi_mux" address="0xf" description="ssm_data[3],onu_data_det3[2],onu_data_det2[1],onu_data_det1[0]" /> <!-- onu_data is default i.e."000"-->
  </node>
  <node id="icap" address="0x100" description="N_SLV_ICAP" fwinfo="endpoint;width=1">
    <node id="iprog_icap" address="0x0"  description="data" permission="w" />
    <node id="icap_status" address="0x1" description="avail[31],prdone[30],prerror[29]" permission="r" />
  </node>
  <node id="gbt1" address="0x108" description="GBT1 (SFP3)" fwinfo="endpoint;width=3">
    <node id="resets" address="0x0"  description="resets" />
    <node id="txctrl" address="0x1" description="tx cfg" />
    <node id="rxctrl" address="0x2" description="rx cfg" />
	<node id="c_spare" address="0x3" description="spare" />
    <node id="status" address="0x4" description="status" permission="r" />
	<node id="Word_count" address="0x5" description="Number of word Received" permission="r" />
    <node id="Error_count" address="0x6" description="Number of errors detected" permission="r" />
    <node id="Correct_count" address="0x7" description="Number of errors corrected" permission="r" />
  </node>
  <node id="gbt2" address="0x110" description="GBT2 (SFP4)" fwinfo="endpoint;width=3">
    <node id="resets" address="0x0"  description="resets" />
    <node id="txctrl" address="0x1" description="tx cfg" />
    <node id="rxctrl" address="0x2" description="rx cfg" />
	<node id="c_spare" address="0x3" description="spare" />
    <node id="status" address="0x4" description="status" permission="r" />
	<node id="Word_count" address="0x5" description="Number of word Received" permission="r" />
    <node id="Error_count" address="0x6" description="Number of errors detected" permission="r" />
    <node id="Correct_count" address="0x7" description="Number of errors corrected" permission="r" />
  </node>
  <node id="ctpemu" address="0x120" description="ctp emulator" fwinfo="endpoint;width=5">
    <node id=         "ctrl" address = "0x0" description =
      "PULSER_EDGE[13],PULSER_ena_for_TPC_RST[12], PULSER_ena_for_TPC_SYNC[11],
      PULSER_ena_for_CAL[10], PULSER_ena_for_PP[9], PULSER_ena_for_PH[8], 
      rst_out_cnts[4],
      LTU_mode[3],
      EMU_TorC[2],
      EMU_run[1],
	  EMU_reset+reset_scalers+reset_HB_counter[0]"	/>
	<node id=        "BCmask_ena" address = "0x1" description =
	  "BCMASK_ena_for_TOF[3], BCMASK_ena_for_CAL[2], BCMASK_ena_for_PP[1], BCMASK_ena_for_PH[0]" />
    <node id=        "TTena" address = "0x2" description =
      "TOF_ena[31],TPC_RST_ena[30],TPC_SYNC_ena[29],EOC_ena[10],SOC_ena[9],EOT_ena[8],SOT_ena[7],
      CAL_ena[6], PP_ena[5],PH_ena[4],HC_enable[3],HBr_enable[2]" />
    <node id=   "rst_N_cnts" address = "0x3" description =
      "rst_TOF_cnt[31],rst_TPC_RST_cnt[30],rst_TPC_SYNC_cnt[29],rst_EOC[10],rst_SOC[9],rst_EOT[8],rst_SOT[7],
      rst_CAL_cnt[6],rst_PP_cnt[5],rst_PH_bc_cnt[4],rst_PH_rnd_cnt[3],rst_HBr_cnt[2]" />
    <node id= "HBr_orbit_rate" address = "0x4" description = "HB reject rate. ORBIT downscaled[15:0]" /> 
    <node id= "HBr_rnd_rate" address = "0x5" description = "HB reject rate. LFSR rnd - not implemented jet" />
    <node id="TF_orbit_rate" address = "0x6" description = "Time Frame rate, ORBIT downscaled[15:0]" />
    <node id=      "HC_rate" address = "0x7" description = "Health Check rate - not implemented jet" />
    <node id=   "PH_bc_rate" address = "0x8" description = "Physics Trigger rate. BC downscale[27:0]" />
    <node id=  "PH_rnd_rate" address = "0x9" description = "Physics Trigger rate. RND downscaled[30:0]" />
    <node id=   "PP_bc_rate" address = "0xa" description = "Prepulse rate, BC downscaled[27:0]" />
    <node id=  "CAL_bc_rate" address = "0xb" description = "Calibration Trigger rate, BC downscaled[27:0]" />
<!--    <node id=  "SOT_tf_rate" address = "0xc" description = "Calibration Trigger rate, TF downscaled[15:0]" /> -->
<!--    <node id=  "EOT_tf_rate" address = "0xd" description = "Calibration Trigger rate, TF downscaled[15:0]" /> -->
<!--    <node id=  "SOC_tf_rate" address = "0xe" description = "Calibration Trigger rate, TF downscaled[15:0]" /> -->
<!--    <node id=  "EOC_tf_rate" address = "0xf" description = "Calibration Trigger rate, TF downscaled[15:0]" /> -->
    <node id="TPC_SYNC_orbit_rate" address = "0x10" description = "TPC SYNC rate,, ORBIT downscaled[15:0]" />
    <node id="TPC_RST_bc_rate" address = "0x11" description = "TPC Reset rate, BC downscaled[27:0]" />
    <node id=  "TOF_bc_rate" address = "0x12" description = "TOF trigger rate, BC downscaled[27:0]" />
    <node id=  "HBr_orbit_n" address = "0x13" description = "HB reject. ORBIT downscale[15:0]" />
    <node id=         "HC_n" address = "0x14" description = "Health Check." />
    <node id=      "PH_bc_n" address = "0x15" description = "N of Physics Triggers, BC downscaled" />
    <node id=     "PH_rnd_n" address = "0x16" description = "N of Physics Trigger. RND downscaled" />
    <node id=      "PP_bc_n" address = "0x17" description = "N of Prepulses" />
    <node id=     "CAL_bc_n" address = "0x18" description = "N of Calibration Triggers" />
<!--    <node id=     "SOT_tf_n" address = "0x19" description = "N of SOT" /> -->
<!--    <node id=     "EOT_tf_n" address = "0x1a" description = "N of EOT" /> -->
<!--    <node id=     "SOC_tf_n" address = "0x1b" description = "N of SOC" /> -->
<!--    <node id=     "EOC_tf_n" address = "0x1c" description = "N of EOC" /> -->
    <node id="TPC_SYNC_orbit_n" address = "0x1d" description = "N of TPC SYNC" />
    <node id= "TPC_RST_bc_n" address = "0x1e" description = "N of TPC Reset" />
    <node id=     "TOF_bc_n" address = "0x1f" description = "N of TOF trigger" />
  </node>
  <node id="bcmasks" address="0x1000" description="12 BC_MASKs" fwinfo="endpoint;width=12">
    <node id="data" address="0x0" mode="block" size="0xdec" description="3564 data words (each 12 bits)" />
  </node>
  <node id="i2cmainttc" address="0x2000" description="I2C main compatible with I2C for TTC-PON" fwinfo="endpoint;width=1">
    <node id="reg" address="0x0" />
    <node id="mux" address="0x1" description="1..11 corresponding to olt1..9,onu,ipbus access to i2c bus" />
  </node>
  <node id="spiadc" address="0x2028" description="SPI master controller: ADC" fwinfo="endpoint;width=3">
    <node id="rs" address="0x0" mode="block" size="0x8" description="regs:d0-d4,ctrl,divider,ss" />
  </node>
  <node id="i2cpll" address="0x2030" description="I2C for si5345 lhc clock" fwinfo="endpoint;width=3">
    <node id="userregs" address="0x0" mode="block" size="0x8" description="regs:pslo,pshi,ctrl,data,cmd_stat" />
  </node>
  <node id="i2cfmcsfp" address="0x2038" description="I2C for si5345 lhc clock" fwinfo="endpoint;width=3">
    <node id="userregs" address="0x0" mode="block" size="0x8" description="regs:pslo,pshi,ctrl,data,cmd_stat" />
  </node>
  <node id="ssm" address="0x2040" description="DDR4 Snapshot Memory" fwinfo="endpoint;width=4">
    <node id="ctrl" address="0x0" mode="block" size="0x8" description="5 control/status regs for r/w access to ddr4" />
   <!-- <node id="data" address="0x8" mode="block" size="0x800" description="data" /> -->  
    <node id="data" address="0x8" mode="non-incremental" size="0x100000" description="data" /> 
  </node>
  <node id="ssmctrl" address="0x2050" description="Control of SSM for R/W from/to ONU clock domain" fwinfo="endpoint;width=3">
    <node id="ssm_control" address="0x0" description="Reset_BC[8], SSM_TxRxData_sel[4], SSM_mode[2], SSM_stop[1], SSM_start[0]"/>
    <node id="ssm_status" address="0x4" permission="r" description="SSM_r_overflow[3], SSM overflow[2], SSM_r_busy[1], SSM_busy[0]"/>
    <node id="ssm_address" address="0x5" permission="r" description="SSM_add[28:0]"/>
	<node id="ssm_r_address" address="0x6" permission="r" description="SSM_r_add[28:0]"/>
  </node>
  <node id="tdg" address="0x2060" description="DDR4 Trigger Data Generator" fwinfo="endpoint;width=4">
    <node id="ctrl" address="0x0" mode="block" size="0x8" description="5 control/status regs for r/w access to ddr4" />
    <node id="data" address="0x8" mode="non-incremental" size="0x100000" description="data" />
  </node>
  <node id="tdgctrl" address="0x2070" description="Control of TDG for R/W from/to OLT clock domain" fwinfo="endpoint;width=3">
    <node id="ssm_control" address="0x0" description="Reset_BC[8], TDG_TxRxData_sel[4], TDG_mode[2], TDG_stop[1], TDG_start[0]"/>
    <node id="ssm_status" address="0x4" permission="r" description="TDG_r_overflow[3], TDG_overflow[2], TDG_r_busy[1], TDG_busy[0]"/>
    <node id="ssm_address" address="0x5" permission="r" description="TDG_w_add[28:0]"/>
    <node id="ssm_r_address" address="0x6" permission="r" description="TDG_r_add[28:0]"/>
  </node>
<!--- unallocated address space of 0x20 words: 0x2040 - 0x205f -->
  <node id="ttcpononu_c" address="0x2100" description="ttcpon user logic regs" fwinfo="endpoint;width=8">
    <node id="cregs" address="0x0" mode="block" size="0x81" description="17 user logic regs" />
  </node>
  <node id="ttcpononu_u" address="0x2200" description="ttcpon user logic regs" fwinfo="endpoint;width=8">
    <node id="uregs" address="0x0" mode="block" size="0x81" description="17 user logic regs" />
  </node>
  <node id="ttcponolt_u1" address="0x2300" description="ttcpon user logic regs" fwinfo="endpoint;width=8">
    <node id="uregs" address="0x0" mode="block" size="0x81" description="17 user logic regs" />
  </node>
  <node id="ttcponolt_u2" address="0x2400" description="ttcpon user logic regs" fwinfo="endpoint;width=8">
    <node id="uregs" address="0x0" mode="block" size="0x81" description="17 user logic regs" />
  </node>
  <node id="ttcponolt_u3" address="0x2500" description="ttcpon user logic regs" fwinfo="endpoint;width=8">
    <node id="uregs" address="0x0" mode="block" size="0x81" description="17 user logic regs" />
  </node>
  <node id="ttcponolt_u4" address="0x2600" description="ttcpon user logic regs" fwinfo="endpoint;width=8">
    <node id="uregs" address="0x0" mode="block" size="0x81" description="17 user logic regs" />
  </node>
  <node id="ttcponolt_u5" address="0x2700" description="ttcpon user logic regs" fwinfo="endpoint;width=8">
    <node id="uregs" address="0x0" mode="block" size="0x81" description="17 user logic regs" />
  </node>
  <node id="ttcponolt_u6" address="0x2800" description="ttcpon user logic regs" fwinfo="endpoint;width=8">
    <node id="uregs" address="0x0" mode="block" size="0x81" description="17 user logic regs" />
  </node>
  <node id="ttcponolt_u7" address="0x2900" description="ttcpon user logic regs" fwinfo="endpoint;width=8">
    <node id="uregs" address="0x0" mode="block" size="0x81" description="17 user logic regs" />
  </node>
  <node id="ttcponolt_u8" address="0x2a00" description="ttcpon user logic regs" fwinfo="endpoint;width=8">
    <node id="uregs" address="0x0" mode="block" size="0x81" description="17 user logic regs" />
  </node>
  <node id="ttcponolt_u9" address="0x2b00" description="ttcpon user logic regs" fwinfo="endpoint;width=8">
    <node id="uregs" address="0x0" mode="block" size="0x81" description="17 user logic regs" />
  </node>
  <node id="ttcponolt_c1" address="0x2c00" description="ttcpon core regs" fwinfo="endpoint;width=7">
    <node id="cregs" address="0x0" mode="block" size="0x80" description="16 OLT/ONU core regs" />
  </node>
  <node id="ttcponolt_c2" address="0x2c80" description="ttcpon core regs" fwinfo="endpoint;width=7">
    <node id="cregs" address="0x0" mode="block" size="0x80" description="16 OLT/ONU core regs" />
  </node>
  <node id="ttcponolt_c3" address="0x2d00" description="ttcpon core regs" fwinfo="endpoint;width=7">
    <node id="cregs" address="0x0" mode="block" size="0x80" description="16 OLT/ONU core regs" />
  </node>
  <node id="ttcponolt_c4" address="0x2d80" description="ttcpon core regs" fwinfo="endpoint;width=7">
    <node id="cregs" address="0x0" mode="block" size="0x80" description="16 OLT/ONU core regs" />
  </node>
  <node id="ttcponolt_c5" address="0x2e00" description="ttcpon core regs" fwinfo="endpoint;width=7">
    <node id="cregs" address="0x0" mode="block" size="0x80" description="16 OLT/ONU core regs" />
  </node>
  <node id="ttcponolt_c6" address="0x2e80" description="ttcpon core regs" fwinfo="endpoint;width=7">
    <node id="cregs" address="0x0" mode="block" size="0x80" description="16 OLT/ONU core regs" />
  </node>
  <node id="ttcponolt_c7" address="0x2f00" description="ttcpon core regs" fwinfo="endpoint;width=7">
    <node id="cregs" address="0x0" mode="block" size="0x80" description="16 OLT/ONU core regs" />
  </node>
  <node id="ttcponolt_c8" address="0x2f80" description="ttcpon core regs" fwinfo="endpoint;width=7">
    <node id="cregs" address="0x0" mode="block" size="0x80" description="16 OLT/ONU core regs" />
  </node>
  <node id="ttcponolt_c9" address="0x3000" description="ttcpon core regs" fwinfo="endpoint;width=7">
    <node id="cregs" address="0x0" mode="block" size="0x80" description="16 OLT/ONU core regs" />
  </node>
  <node id="FLASH_SPI_Ram_0" address="0x3200" description="SPI_RAM_0"  tags="slave" fwinfo = "endpoint;width=9"> 
    <node id="Select"    address="0x0"/> <!-- just ignore if only one Flash -->
    <node id="Num_Words" address="0x2"/> <!-- number of bytes in case of "BYTE_SPI => TRUE" -->
    <node id="Command"   address="0x3"> <!-- transition to "1" -> start, then we need to clear it -->
      <node id="Do_it" mask="0x1"/>
    </node>
    <node id="Status"    address="0x4" permission="r">
      <node id="Busy" mask="0x1"/>     <!-- SPI controller BUSY - active in log.1 -->
    </node>
    <node id="Key_Lock"  address="0x80"> 
      <node id="Key"  mask="0x7FFFFFFC"/> <!-- lock counter i.e. one access = 1 count -->
      <node id="Lock" mask="0x2"/> <!-- lock is in use, it should be set be RMW trasaction -->
      <node id="Terr" mask="0x1"/> <!-- lock timeout error i.e. transaction not finished in defined time -->
    </node>
    <node id="Timeout"   address="0x81"/> <!-- 32-bit counter in mili seconds -->
    <node id="Outgoing"  address="0x100" mode="block" size="0x80" description="128word RAM" /> <!-- input command[7:0], address[23:0], data[31:0} -->
    <node id="Incoming"  address="0x180" mode="block" size="0x80" description="128word RAM" /> <!-- rubbish [31:0] + data [31:0] -->
  </node>
  <node id="FLASH_SPI_Ram_1" address="0x3400" description="SPI_RAM_1"  tags="slave" fwinfo = "endpoint;width=9"> 
    <node id="Select"    address="0x0"/> <!-- just ignore if only one Flash -->
    <node id="Num_Words" address="0x2"/> <!-- number of bytes in case of "BYTE_SPI => TRUE" -->
    <node id="Command"   address="0x3"> <!-- transition to "1" -> start, then we need to clear it -->
      <node id="Do_it" mask="0x1"/>
    </node>
    <node id="Status"    address="0x4" permission="r">
      <node id="Busy" mask="0x1"/>     <!-- SPI controller BUSY - active in log.1 -->
    </node>
    <node id="Key_Lock"  address="0x80"> 
      <node id="Key"  mask="0x7FFFFFFC"/> <!-- lock counter i.e. one access = 1 count -->
      <node id="Lock" mask="0x2"/> <!-- lock is in use, it should be set be RMW trasaction -->
      <node id="Terr" mask="0x1"/> <!-- lock timeout error i.e. transaction not finished in defined time -->
    </node>
    <node id="Timeout"   address="0x81"/> <!-- 32-bit counter in mili seconds -->
    <node id="Outgoing"  address="0x100" mode="block" size="0x80" description="128word RAM" /> <!-- input command[7:0], address[23:0], data[31:0} -->
    <node id="Incoming"  address="0x180" mode="block" size="0x80" description="128word RAM" /> <!-- rubbish [31:0] + data [31:0] -->
  </node>
  <node id="outcnts" address="0x3600" description="Counters for outgoing signals" fwinfo="endpoint;width=6">
    <node id="TTcnts" address="0x0" mode="block" size="0x40" permission="r" description="32 Trigger Type counters + BC counter + 240MHz BC counter" />
  </node>
   <node id="ttc" address="0x3650" description="N_SLV_TTC" fwinfo="endpoint;width=4">
    <node id="chbdata" address="0x0"  description="Chanel B data" />
    <node id="ctrl" address="0x1"  description="control: resert[0]; busy_IN_enable[1]; mode[7:4]: 0x1: TTC, 0x2: TRD, 0x3: CPV; TTC-AB_delay[15:8]: 0x10: no delay, 0x02: 1/2 BC delay" />
    <node id="LLprot" address="0x2"  description="TTC/GBT: L0-L1 protection interval; TRD: L0-L0 protection interval" />
    <node id="L1reject" address="0x3"  description="L1 reject rate" />
    <node id="CAL_rate" address="0x4"  description="TRD cal rate" />
    <node id="write_spare1" address="0x5"  description="write spare 1" />
    <node id="write_spare2" address="0x6"  description="write spare 2" />
    <node id="write_spare3" address="0x7"  description="write spare 3" />
    <node id="status" address="0x8" permission="r" description="status bits" />
    <node id="L0pre_count" address="0x9" permission="r" description="L0 pre-trigger counter" />
    <node id="L0_count" address="0xa" permission="r" description="L0 trigger counter" />
    <node id="L1_count" address="0xb" permission="r" description="L1 trigger counter" />
    <node id="Orbit_count" address="0xc" permission="r" description="Orbit trigger counter" />
    <node id="PP_count" address="0xd" permission="r" description="PP trigger counter" />
    <node id="L1r_count" address="0xe" permission="r" description="L1 reject counter" />
    <node id="CAL_count" address="0xf" permission="r" description="CAL counter" />
  </node>
  <node id="leco1" address="0x3700" description="Link error counters for OLT_1 upstream" fwinfo="endpoint;width=6">
    <node id="data" address="0x0" mode="block" size="0x40" permission="r" description="64 Link Error counters" />
  </node>
  <node id="cdc_phase_scan" address="0x3740" fwinfo="endpoint;width=1">
    <node id="cdc_ctrl" address="0x0" /> 
    <node id="cdc_status" address="0x1" permission="r" /> 
    <node id="test" address="0x2" description="bad addr" /> 
  </node>
</node>

Cheers, Anton

@tswilliams
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Hi,

Based on that MD5 hash, I think you have an old version of the script (commit 8a92791286e7fc97efe00e7d063a3b5332b374df); since that version of the script, we've fixed some bugs in it. The latest version of the script on the feature/193-addr-table-checks branch reports the following error messages for the quoted address table:

ERROR	: Endpoint node <<cdc_phase_scan>> (base address 0x3740, width 1) has a sub-node <<cdc_phase_scan.test>> (base address 0x3742, size 0x1) that overflows its address space
ERROR	: Node errors detected, exiting early before writing output

... and its exit code is 2.

To try the latest version of the script, can you run the following commands?

curl https://raw.githubusercontent.com/ipbus/ipbus-software/9c826b4c2f47f93d0beb531c10e4c8bb305fc379/uhal/tools/scripts/gen_ipbus_addr_decode -o /tmp/gen_ipbus_addr_decode
chmod u+x /tmp/gen_ipbus_addr_decode
/tmp/gen_ipbus_addr_decode /path/to/addr_table.xml

Cheers,
Tom

@juskoa
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juskoa commented May 14, 2020

Yes, works fine:

ERROR	: Endpoint node <<cdc_phase_scan>> (base address 0x3740, width 1) has a sub-node <<cdc_phase_scan.test>> (base address 0x3742, size 0x1) that overflows its address space
ERROR	: Node errors detected, exiting early before writing output
[trigger@acsl3 vhd]$ echo $?
2

Thank you for patience, Cheers, Anton

@tswilliams
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Hi @mkrivda @juskoa

The fixes for this ticket have now been included in a new software tag - v2.7.4

Cheers,
Tom

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4 participants