GitHub - irsyadhanif/EE480-Assignment-5: A superscalar processor made in verilog

A superscalar processor in Verilog

Name		Name	Last commit message	Last commit date
Latest commit History 23 Commits
bu		bu
testcode_files		testcode_files
.datamem.vmem.swp		.datamem.vmem.swp
.isa.asm.swp		.isa.asm.swp
.loQDon.v.swp		.loQDon.v.swp
.mainmem.vmem.swp		.mainmem.vmem.swp
.mainmem_16.vmem.swp		.mainmem_16.vmem.swp
.oldProject.v.swp		.oldProject.v.swp
.regfile.vmem.swp		.regfile.vmem.swp
.testCode.asm.swp		.testCode.asm.swp
.vimperatorrc		.vimperatorrc
.vimrc		.vimrc
.zshrc		.zshrc
README.md		README.md
a		a
datamem.vmem		datamem.vmem
dumpfile.vcd		dumpfile.vcd
isa.asm		isa.asm
loQDon		loQDon
loQDon.v		loQDon.v
loQDon.v.new1		loQDon.v.new1
mainmem.vmem		mainmem.vmem
mainmem_16.vmem		mainmem_16.vmem
nitebha-doch-cha.pdf		nitebha-doch-cha.pdf
notes.pdf		notes.pdf
oldProject		oldProject
oldProject.v		oldProject.v
regfile.vmem		regfile.vmem
super.v		super.v
testCode.asm		testCode.asm
testcode.html		testcode.html

irsyadhanif/EE480-Assignment-5