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model branches as normal lines, because it's not possible to open dis…
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…symmetrical branches and to short-circuit them
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@CBiasuzzi
CBiasuzzi committed Apr 6, 2018
1 parent 11e03ab commit 66e0a9f
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49 changes: 44 additions & 5 deletions ...ag-ech-export/src/main/java/eu/itesla_project/iidm/eurostag/export/EurostagEchExport.java
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Expand Up @@ -198,14 +198,53 @@ private void createLines(EsgNetwork esgNetwork, EsgGeneralParameters parameters)
LOGGER.warn("not in main component, skipping Line: {}", l.getId());
continue;
}

// It is better to model branches as -normal- lines because it is impossible to open dissymmetrical branches and to do short-circuit on them
// Therefore, normal lines are created:
// - If the G and B are the same on each side of the line, even if the G are not 0
// - If the B are not the same but the G are 0
// The code could be extended to handle the case where the B are not the same and the G are not the same
ConnectionBus bus1 = ConnectionBus.fromTerminal(l.getTerminal1(), config, fakeNodes);
ConnectionBus bus2 = ConnectionBus.fromTerminal(l.getTerminal2(), config, fakeNodes);
// if the admittance are the same in the both side of PI line model
if (Math.abs(l.getG1() - l.getG2()) < G_EPSILON && Math.abs(l.getB1() - l.getB2()) < B_EPSILON) {
//...create a simple line
if (Math.abs(l.getG1() - l.getG2()) < G_EPSILON
&& (Math.abs(l.getB1() - l.getB2()) < B_EPSILON
|| (Math.abs(l.getG1()) < G_EPSILON && Math.abs(l.getG2()) < G_EPSILON))) {
ConnectionBus bNode = null;
float b;
float diffB = 0f;
float g = (l.getG1() + l.getG2()) / 2.0f;
float vNom = 0f;
if (l.getB1() < l.getB2() - B_EPSILON) {
bNode = bus2;
b = l.getB1();
diffB = l.getB2() - l.getB1();
vNom = l.getTerminal2().getVoltageLevel().getNominalV();
} else if (l.getB2() < l.getB1() - B_EPSILON) {
bNode = bus1;
b = l.getB2();
diffB = l.getB1() - l.getB2();
vNom = l.getTerminal1().getVoltageLevel().getNominalV();
} else {
b = (l.getB1() + l.getB2()) / 2.0f;
}

esgNetwork.addLine(createLine(l.getId(), bus1, bus2, l.getTerminal1().getVoltageLevel().getNominalV(),
l.getR(), l.getX(), l.getG1(), l.getB1(), parameters));
l.getR(), l.getX(), g, b, parameters));

if (bNode != null) {
//create a dummy shunt attached to bNode
String fictionalShuntId = "FKSH" + l.getId();
addToDictionary(fictionalShuntId, dictionary, EurostagNamingStrategy.NameType.BANK);

int ieleba = 1;
float plosba = 0.f;
float rcapba = vNom * vNom * diffB;
int imaxba = 1;
EsgCapacitorOrReactorBank.RegulatingMode xregba = EsgCapacitorOrReactorBank.RegulatingMode.NOT_REGULATING;

esgNetwork.addCapacitorsOrReactorBanks(new EsgCapacitorOrReactorBank(new Esg8charName(dictionary.getEsgId(fictionalShuntId)),
new Esg8charName(dictionary.getEsgId(bNode.getId())),
ieleba, plosba, rcapba, imaxba, xregba));
}
} else {
EsgBranchConnectionStatus status = getStatus(bus1, bus2);
if (status.equals(EsgBranchConnectionStatus.CLOSED_AT_BOTH_SIDE)) {
Expand Down
65 changes: 62 additions & 3 deletions ...ch-export/src/test/java/eu/itesla_project/iidm/eurostag/export/EurostagEchExportTest.java
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Original file line number Diff line number Diff line change
Expand Up @@ -7,12 +7,15 @@
package eu.itesla_project.iidm.eurostag.export;

import com.google.common.io.CharStreams;
import com.powsybl.iidm.network.test.HvdcTestNetwork;
import eu.itesla_project.eurostag.network.EsgGeneralParameters;
import eu.itesla_project.eurostag.network.EsgSpecialParameters;
import com.powsybl.iidm.network.Bus;
import com.powsybl.iidm.network.Network;
import com.powsybl.iidm.network.TopologyKind;
import com.powsybl.iidm.network.VoltageLevel;
import com.powsybl.iidm.network.test.EurostagTutorialExample1Factory;
import com.powsybl.iidm.network.test.HvdcTestNetwork;
import com.powsybl.iidm.network.test.SvcTestCaseFactory;
import eu.itesla_project.eurostag.network.EsgGeneralParameters;
import eu.itesla_project.eurostag.network.EsgSpecialParameters;
import org.joda.time.LocalDate;
import org.junit.Test;

Expand Down Expand Up @@ -74,4 +77,60 @@ public void testHVDC() throws IOException {
test(network, "/eurostag-hvdc-test.ech", LocalDate.parse("2016-01-01"), specialParameters);
}

private void addLine(Network network, VoltageLevel vlhv1, VoltageLevel vlhv2, String idLine, float g1, float g2, float b1, float b2) {
Bus nhv1 = vlhv1.getBusBreakerView().newBus()
.setId("N1" + idLine)
.add();
Bus nhv2 = vlhv2.getBusBreakerView().newBus()
.setId("N2" + idLine)
.add();
network.newLine()
.setId(idLine)
.setVoltageLevel1(vlhv1.getId())
.setBus1(nhv1.getId())
.setConnectableBus1(nhv1.getId())
.setVoltageLevel2(vlhv2.getId())
.setBus2(nhv2.getId())
.setConnectableBus2(nhv2.getId())
.setR(3)
.setX(33)
.setG1(g1)
.setB1(b1)
.setG2(g2)
.setB2(b2)
.add();
}

@Test
public void testLines() throws IOException {
Network network = EurostagTutorialExample1Factory.create();
VoltageLevel vlhv1 = network.getSubstation("P1").newVoltageLevel()
.setId("VL1")
.setNominalV(380)
.setTopologyKind(TopologyKind.BUS_BREAKER)
.add();
VoltageLevel vlhv2 = network.getSubstation("P2").newVoltageLevel()
.setId("VL2")
.setNominalV(380)
.setTopologyKind(TopologyKind.BUS_BREAKER)
.add();

float bTest1 = EurostagEchExport.B_EPSILON * 2f;

//G and B are the same on each side, G are 0
addLine(network, vlhv1, vlhv2, "L1", 0f, 0f, 0f, 0f);
addLine(network, vlhv1, vlhv2, "L2", 0f, 0f, bTest1, bTest1);
//B are not the same, G are 0
addLine(network, vlhv1, vlhv2, "L3", 0f, 0f, bTest1, 0); // dummy shunt expected in the .ech
addLine(network, vlhv1, vlhv2, "L4", 0f, 0f, 0, bTest1); // dummy shunt expected in the .ech
addLine(network, vlhv1, vlhv2, "L5", 0f, 0f, EurostagEchExport.B_EPSILON / 2f, 0);
addLine(network, vlhv1, vlhv2, "L6", 0f, 0f, 0, EurostagEchExport.B_EPSILON / 2f);
//B are not the same, G are not 0
addLine(network, vlhv1, vlhv2, "L7", 1f, 0f, bTest1, 0);
addLine(network, vlhv1, vlhv2, "L8", 0f, 1f, bTest1, 0);

EsgSpecialParameters specialParameters = new EsgSpecialParameters();
test(network, "/eurostag-tutorial-example1_lines.ech", LocalDate.parse("2016-03-01"), specialParameters);
}

}
73 changes: 73 additions & 0 deletions eurostag-ech-export/src/test/resources/eurostag-tutorial-example1_lines.ech
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Original file line number Diff line number Diff line change
@@ -0,0 +1,73 @@
HEADER 01/03/16 5.1

B

9 1 0 0 1 1 20 0.005 4 100. 1 1

SP INPVPQ 2
SP THMAX 0.100000
SP EMAXF 0.100000
SP ZMIN 0.000200
SP RAMIN 0.800000
SP RAMAX 1.200000
SP TOLPLO 0.001000

GC sim1/InitialState

AA FA
AA FR

1FAFAKENOD1 380. 1. 0. 0. 0.
1FAFAKENOD2 380. 1. 0. 0. 0.
1FRN1L1 380. 1. 0. 0. 0.
1FRN1L2 380. 1. 0. 0. 0.
1FRN1L3 380. 1. 0. 0. 0.
1FRN1L4 380. 1. 0. 0. 0.
1FRN1L5 380. 1. 0. 0. 0.
1FRN1L6 380. 1. 0. 0. 0.
1FRN1L7 380. 1. 0. 0. 0.
1FRN1L8 380. 1. 0. 0. 0.
1FRN2L1 380. 1. 0. 0. 0.
1FRN2L2 380. 1. 0. 0. 0.
1FRN2L3 380. 1. 0. 0. 0.
1FRN2L4 380. 1. 0. 0. 0.
1FRN2L5 380. 1. 0. 0. 0.
1FRN2L6 380. 1. 0. 0. 0.
1FRN2L7 380. 1. 0. 0. 0.
1FRN2L8 380. 1. 0. 0. 0.
1FRNGEN 24. 1. 0. 0. 0.
5 NGEN 0.
1FRNHV1 380. 1. 0. 0. 0.
1FRNHV2 380. 1. 0. 0. 0.
1FRNLOAD 150. 1. 0. 0. 0.

3 N1L1 N2L1 1 0.002078 0.022853 0. 0. 100. 0. 0.
3 N1L2 N2L2 1 0.002078 0.022853 0. 0.002888 100. 0. 0.
3 N1L3 N2L3 1 0.002078 0.022853 0. 0. 100. 0. 0.
3 N1L4 N2L4 1 0.002078 0.022853 0. 0. 100. 0. 0.
3 N1L5 N2L5 1 0.002078 0.022853 0. 0.000361 100. 0. 0.
3 N1L6 N2L6 1 0.002078 0.022853 0. 0.000361 100. 0. 0.
3 NHV1 NHV2 1 0.002078 0.022853 0. 0.278692 100. 0. 0.
3 NHV1 NHV2 2 0.002078 0.022853 0. 0.278692 100. 0. 0.

P N1L7 N2L7 1 0.002078 0.022853 1444. 0.002888 100.
P 0.002078 0.022853 0. 0.
P N1L8 N2L8 1 0.002078 0.022853 0. 0.002888 100.
P 0.002078 0.022853 1444. 0.

48NGEN NHV1 1 100.0.018462 0. 0. 1. 0. 0.
48 1 1 N
48 1 22.8 380. 0.769231 0.
48NHV2 NLOAD 1 100. 0.021 0. 0. 1. 0. 0.
48 2 2 NLOAD 158. V
48 1 446.4633 150. 1.8 0.
48 2 379.4938 150. 1.8 0.
48 3 329.9946 150. 1.8 0.

CH LOAD Y NLOAD 0. 0. 600. 0. 0. 200. 0. 0.

G GEN Y NGEN -9999.99 607. 9999.99 -9999.99 301. 9999.99 V 24.5 NGEN 1. 0. 0.

C FKSHL3 N1L3 1 0. 0.2888 1 N 0. 0. 0.
C FKSHL4 N2L4 1 0. 0.2888 1 N 0. 0. 0.

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