Fixed cpu tests

src/cpu/cpu.test.zig

@@ -2,10 +2,8 @@ const std = @import("std");
 const expect = std.testing.expect;
 const allocator = std.testing.allocator;
 
-const Cpu = @import("./cpu.zig").Cpu;
-const Bus = @import("../bus//bus.zig");
-const BusCallback = Bus.BusCallback;
-const Ram = @import("../bus/ram.zig").Ram;
+const Cpu = @import("./cpu.zig");
+const MainBus = @import("./main_bus.zig");
 
 const OpCodeError = error {
     UnexpectedBehaviour
@@ -33,24 +31,20 @@ const TestEnv = struct {
         const Cycle = struct {u16, u8, []const u8};
     };
 
-    bus: Bus,
-    cpu: Cpu(null),
+    bus: MainBus,
+    cpu: Cpu,
     unused: bool = false,
 
-    fn init(ram: *Ram(0x10000)) !TestEnv {
+    fn init() !TestEnv {
         return .{
-            .bus = try Bus.init(allocator, 0x10000, ram.busCallback()),
-            .cpu = undefined,
+            .bus = try MainBus.testInit(allocator),
+            .cpu = try Cpu.init(),
         };
     }
 
-    fn initCpu(self: *Self) void {
-        self.cpu = Cpu(null).initWithTestBus(&self.bus, &self.unused, &self.unused) catch unreachable;
-    }
-
     fn deinit(self: *Self) void {
         self.cpu.deinit();
-        self.bus.deinit(allocator);
+        self.bus.testDeinit();
     }
 
     fn setState(env: *TestEnv, state: CpuState) void {
@@ -62,7 +56,7 @@ const TestEnv = struct {
         env.cpu.p = @bitCast(state.p);
 
         for (state.ram orelse unreachable) |data| {
-            env.bus.writeByte(data[0], data[1]);
+            env.bus.write(data[0], data[1]);
         }
         env.cpu.wait_cycles = 0;
     }
@@ -77,7 +71,7 @@ const TestEnv = struct {
         is_correct = is_correct and @as(u8, @bitCast(env.cpu.p)) == state.p;
 
         for (state.ram orelse unreachable) |data| {
-            is_correct = is_correct and env.bus.readByte(data[0]) == data[1];
+            is_correct = is_correct and env.bus.read(data[0]) == data[1];
         }
 
         return is_correct;
@@ -97,7 +91,7 @@ const TestEnv = struct {
             },
         });
         for (expected.ram orelse unreachable) |data| {
-            const value = env.bus.readByte(data[0]);
+            const value = env.bus.read(data[0]);
             std.debug.print("\t${X:0>4}: 0x{X:0>2}\tEx: 0x{X:0>2}\n", .{data[0], value, data[1]});
         }
     }
@@ -112,10 +106,9 @@ const TestEnv = struct {
         defer tests_json.deinit();
 
         // Prepare the test environment
-        var test_memory = Ram(0x10000){};
-        var test_env = try TestEnv.init(&test_memory);
+        var test_env = try TestEnv.init();
+        test_env.cpu.connectMainBus(&test_env.bus);
         defer test_env.deinit();
-        test_env.initCpu();
 
         var num_not_passed: u16 = 0;
 

src/cpu/main_bus.zig

@@ -8,7 +8,11 @@ const Controllers = @import("../controllers.zig");
 
 const Self = @This();
 
+allocator: Allocator,
+
 cpu_ram: [0x800]u8,
+test_ram: []u8,
+
 ppu: *Ppu,
 apu: *Apu,
 controllers: *Controllers,
@@ -17,24 +21,59 @@ rom: Rom,
 nmi: bool = false,
 irq: bool = false,
 
+read_fn: *const fn (self: *Self, address: u16) u8,
+write_fn: *const fn (self: *Self, address: u16, value: u8) void,
+
 pub fn init(ppu: *Ppu, apu: *Apu, controllers: *Controllers) Self {
     var main_bus: Self = .{
+        .allocator = undefined,
         .cpu_ram = undefined,
+        .test_ram = undefined,
         .ppu = ppu,
         .apu = apu,
         .controllers = controllers,
-        .rom = undefined
+        .rom = undefined,
+        .read_fn = normalRead,
+        .write_fn = normalWrite
     };
     @memset(main_bus.cpu_ram[0..], 0);
     return main_bus;
 }
 
+pub fn testInit(allocator: Allocator) !Self {
+    var main_bus: Self = .{
+        .allocator = allocator,
+        .cpu_ram = undefined,
+        .test_ram = try allocator.alloc(u8, 0x10000),
+        .ppu = undefined,
+        .apu = undefined,
+        .controllers = undefined,
+        .rom = undefined,
+        .read_fn = testRead,
+        .write_fn = testWrite
+    };
+    @memset(main_bus.test_ram[0..], 0);
+    return main_bus;
+}
+
+pub fn testDeinit(self: *Self) void {
+    self.allocator.free(self.test_ram);
+}
+
 pub fn reset(self: *Self) void {
     self.irq = false;
     self.nmi = false;
 }
 
-pub fn read(self: *Self, address: u16) u8 {
+pub inline fn read(self: *Self, address: u16) u8 {
+    return self.read_fn(self, address);
+}
+
+pub inline fn write(self: *Self, address: u16, value: u8) void {
+    return self.write_fn(self, address, value);
+}
+
+fn normalRead(self: *Self, address: u16) u8 {
     return switch (address) {
         0...0x1FFF => self.cpu_ram[address % 0x800],
         0x2000...0x3FFF => switch (address % 8) {
@@ -57,7 +96,7 @@ pub fn read(self: *Self, address: u16) u8 {
     };
 }
 
-pub fn write(self: *Self, address: u16, value: u8) void {
+fn normalWrite(self: *Self, address: u16, value: u8) void {
     switch (address) {
         0...0x1FFF => {
             self.cpu_ram[address % 0x800] = value;
@@ -110,6 +149,14 @@ pub fn write(self: *Self, address: u16, value: u8) void {
     }
 }
 
+fn testRead(self: *Self, address: u16) u8 {
+    return self.test_ram[address];
+}
+
+fn testWrite(self: *Self, address: u16, value: u8) void {
+    self.test_ram[address] = value;
+}
+
 pub fn setRom(self: *Self, rom: Rom) void {
     self.rom = rom;
 }