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Both 8-bit headers hooked up. Random number source.
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@jamesbowman
jamesbowman committed Sep 25, 2015
1 parent 13dac8e commit 1e8708f
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Showing 2 changed files with 107 additions and 13 deletions.
18 changes: 18 additions & 0 deletions j1a/icestorm/j1a.pcf
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Original file line number Diff line number Diff line change
Expand Up @@ -22,3 +22,21 @@ set_io PIO1_06 87
set_io PIO1_07 88
set_io PIO1_08 90
set_io PIO1_09 91

set_io PIO0_02 112
set_io PIO0_03 113
set_io PIO0_04 114
set_io PIO0_05 115
set_io PIO0_06 116
set_io PIO0_07 117
set_io PIO0_08 118
set_io PIO0_09 119

set_io PIO2_10 44
set_io PIO2_11 45
set_io PIO2_12 47
set_io PIO2_13 48
set_io PIO2_14 56
set_io PIO2_15 60
set_io PIO2_16 61
set_io PIO2_17 62
102 changes: 89 additions & 13 deletions j1a/icestorm/j1a.v
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Original file line number Diff line number Diff line change
Expand Up @@ -102,6 +102,7 @@ module outpin(
.D_IN_0(rd));
endmodule


module top(input clk, output D1, output D2, output D3, output D4, output D5,

output TXD, // UART TX
Expand All @@ -121,6 +122,24 @@ module top(input clk, output D1, output D2, output D3, output D4, output D5,
inout PIO1_08, // PMOD 7
inout PIO1_09, // PMOD 8

inout PIO0_02, // HDR1 1
inout PIO0_03, // HDR1 2
inout PIO0_04, // HDR1 3
inout PIO0_05, // HDR1 4
inout PIO0_06, // HDR1 5
inout PIO0_07, // HDR1 6
inout PIO0_08, // HDR1 7
inout PIO0_09, // HDR1 8

inout PIO2_10, // HDR2 1
inout PIO2_11, // HDR2 2
inout PIO2_12, // HDR2 3
inout PIO2_13, // HDR2 4
inout PIO2_14, // HDR2 5
inout PIO2_15, // HDR2 6
inout PIO2_16, // HDR2 7
inout PIO2_17, // HDR2 8

output PIO1_18, // IR TXD
input PIO1_19, // IR RXD
output PIO1_20, // IR SD
Expand Down Expand Up @@ -161,6 +180,8 @@ module top(input clk, output D1, output D2, output D3, output D4, output D5,

// ###### IO SIGNALS ####################################

`define EASE_IO_TIMING
`ifdef EASE_IO_TIMING
reg io_wr_, io_rd_;
reg [15:0] dout_;
reg [15:0] io_addr_;
Expand All @@ -170,12 +191,16 @@ module top(input clk, output D1, output D2, output D3, output D4, output D5,
if (io_rd | io_wr)
io_addr_ <= mem_addr;
end
`else
wire io_wr_ = io_wr, io_rd_ = io_rd;
wire [15:0] dout_ = dout;
wire [15:0] io_addr_ = mem_addr;
`endif

// ###### PMOD ##########################################

reg [7:0] pmod_dir; // 1:output, 0:input
wire [7:0] pmod_in;
wire w0 = io_wr_ & io_addr_[0];

ioport _mod (.clk(clk),
.pins({PIO1_09, PIO1_08, PIO1_07, PIO1_06, PIO1_05, PIO1_04, PIO1_03, PIO1_02}),
Expand All @@ -184,6 +209,30 @@ module top(input clk, output D1, output D2, output D3, output D4, output D5,
.rd(pmod_in),
.dir(pmod_dir));

// ###### HDR1 ##########################################

reg [7:0] hdr1_dir; // 1:output, 0:input
wire [7:0] hdr1_in;

ioport _hdr1 (.clk(clk),
.pins({PIO0_09, PIO0_08, PIO0_07, PIO0_06, PIO0_05, PIO0_04, PIO0_03, PIO0_02}),
.we(io_wr_ & io_addr_[4]),
.wd(dout_[7:0]),
.rd(hdr1_in),
.dir(hdr1_dir));

// ###### HDR2 ##########################################

reg [7:0] hdr2_dir; // 1:output, 0:input
wire [7:0] hdr2_in;

ioport _hdr2 (.clk(clk),
.pins({PIO2_17, PIO2_16, PIO2_15, PIO2_14, PIO2_13, PIO2_12, PIO2_11, PIO2_10}),
.we(io_wr_ & io_addr_[6]),
.wd(dout_[7:0]),
.rd(hdr2_in),
.dir(hdr2_dir));

// ###### UART ##########################################

wire uart0_valid, uart0_busy;
Expand All @@ -206,40 +255,63 @@ module top(input clk, output D1, output D2, output D3, output D4, output D5,
wire [4:0] LEDS;
wire w4 = io_wr_ & io_addr_[2];

wire [4:0] PIOS;
wire w8 = io_wr_ & io_addr_[3];

outpin led0 (.clk(clk), .we(w4), .pin(D5), .wd(dout_[0]), .rd(LEDS[0]));
outpin led1 (.clk(clk), .we(w4), .pin(D4), .wd(dout_[1]), .rd(LEDS[1]));
outpin led2 (.clk(clk), .we(w4), .pin(D3), .wd(dout_[2]), .rd(LEDS[2]));
outpin led3 (.clk(clk), .we(w4), .pin(D2), .wd(dout_[3]), .rd(LEDS[3]));
outpin led4 (.clk(clk), .we(w4), .pin(D1), .wd(dout_[4]), .rd(LEDS[4]));

wire [4:0] PIOS;
wire w8 = io_wr_ & io_addr_[3];

outpin pio0 (.clk(clk), .we(w8), .pin(PIOS_03), .wd(dout_[0]), .rd(PIOS[0]));
outpin pio1 (.clk(clk), .we(w8), .pin(PIOS_02), .wd(dout_[1]), .rd(PIOS[1]));
outpin pio2 (.clk(clk), .we(w8), .pin(PIOS_00), .wd(dout_[2]), .rd(PIOS[2]));
outpin pio3 (.clk(clk), .we(w8), .pin(PIO1_18), .wd(dout_[3]), .rd(PIOS[3]));
outpin pio4 (.clk(clk), .we(w8), .pin(PIO1_20), .wd(dout_[4]), .rd(PIOS[4]));

// ###### RING OSCILLATOR ###############################

wire [1:0] buffers_in, buffers_out;
assign buffers_in = {buffers_out[0:0], ~buffers_out[1]};
SB_LUT4 #(
.LUT_INIT(16'd2)
) buffers [1:0] (
.O(buffers_out),
.I0(buffers_in),
.I1(1'b0),
.I2(1'b0),
.I3(1'b0)
);
wire random = buffers_out[0];

// ###### IO PORTS ######################################

/* bit READ WRITE
0001 0 PMOD rd PMOD wr
0002 1 PMOD direction
0004 2 LEDS
0008 3 misc.out
0800 11 sb_warmboot
1000 12 UART RX UART TX
2000 13 misc.in
/* bit mode device
0001 0 r/w PMOD GPIO
0002 1 r/w PMOD direction
0004 2 r/w LEDS
0008 3 r/w misc.out
0010 4 r/w HDR1 GPIO
0020 5 r/w HDR1 direction
0040 6 r/w HDR2 GPIO
0080 7 r/w HDR2 direction
0800 11 w sb_warmboot
1000 12 r/w UART RX, UART TX
2000 13 r misc.in
*/

assign io_din =
(io_addr_[ 0] ? {8'd0, pmod_in} : 16'd0) |
(io_addr_[ 1] ? {8'd0, pmod_dir} : 16'd0) |
(io_addr_[ 2] ? {11'd0, LEDS} : 16'd0) |
(io_addr_[ 3] ? {11'd0, PIOS} : 16'd0) |
(io_addr_[ 4] ? {8'd0, hdr1_in} : 16'd0) |
(io_addr_[ 5] ? {8'd0, hdr1_dir} : 16'd0) |
(io_addr_[ 6] ? {8'd0, hdr2_in} : 16'd0) |
(io_addr_[ 7] ? {8'd0, hdr2_dir} : 16'd0) |
(io_addr_[12] ? {8'd0, uart0_data} : 16'd0) |
(io_addr_[13] ? {12'd0, PIO1_19, PIOS_01, uart0_valid, !uart0_busy} : 16'd0);
(io_addr_[13] ? {11'd0, random, PIO1_19, PIOS_01, uart0_valid, !uart0_busy} : 16'd0);

reg boot, s0, s1;

Expand All @@ -252,6 +324,10 @@ module top(input clk, output D1, output D2, output D3, output D4, output D5,
always @(posedge clk) begin
if (io_wr_ & io_addr_[1])
pmod_dir <= dout_[7:0];
if (io_wr_ & io_addr_[5])
hdr1_dir <= dout_[7:0];
if (io_wr_ & io_addr_[7])
hdr2_dir <= dout_[7:0];
if (io_wr_ & io_addr_[11])
{boot, s1, s0} <= dout_[2:0];
end
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