Quickfix821 (#127)

* a few minor fixes
jameshegarty · Oct 1, 2018 · f6d19f9 · f6d19f9
1 parent 392e119
commit f6d19f9
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Showing 5 changed files with 17 additions and 13 deletions.
diff --git a/examples/harnessTerraSOC.t b/examples/harnessTerraSOC.t
@@ -8,8 +8,12 @@ local data = macro(function(i) return `i._0 end)
 local valid = macro(function(i) return `i._1 end)
 local ready = macro(function(i) return `i._2 end)
 
---V = terralib.includec("/home/jhegarty/rigel/platform/verilatorSOC/harness.h")
-V = terralib.includec("..//platform/verilatorSOC/harness.h")
+function script_path()
+  local str = debug.getinfo(2, "S").source:sub(2)
+  return str:match("(.*/)")
+end
+
+V = terralib.includec(script_path().."../platform/verilatorSOC/harness.h")
 
 local Ctmp = terralib.includecstring [[
                                         #include <stdio.h>

diff --git a/misc/rigelSimple.lua b/misc/rigelSimple.lua
@@ -417,7 +417,7 @@ function RS.writePixels(input,id,imageSize,V,DIR)
     TY = input.type
   end
 
-  local mod = RS.modules.fwriteSeq{type=TY, filename=DIR.."/dbg_terra_"..id..".raw", filenameVerilog=DIR.."/dbg_verilator_"..id..".raw"}
+  local mod = RS.modules.fwriteSeq{type=TY, filename=DIR.."/dbg_terra_"..id..".raw", filenameVerilog=DIR.."/dbg_verilatorSOC_"..id..".raw"}
 
   if R.isHandshake(input.type) then
      mod = RS.HS(mod)

diff --git a/src/generators.lua b/src/generators.lua
@@ -371,12 +371,12 @@ function(args)
   end
 end)
 
-generators.ReduceSeq = R.newGenerator("generators","Reduce",{"type","rigelFunction","number"},{},
+generators.ReduceSeq = R.newGenerator("generators","ReduceSeq",{"type","rigelFunction","number","rate"},{},
 function(args)
 
   local mod
   if R.isGenerator(args.rigelFunction) then
-    mod = args.rigelFunction{types.tuple{args.type,args.type}}
+    mod = args.rigelFunction{types.tuple{args.type,args.type},args.rate}
     assert( R.isModule(mod) )
   else
     assert(false)
@@ -412,7 +412,7 @@ function(args)
   return C.fassert(args.string,args.type)
 end)
 
-generators.WriteBurst = R.newGenerator("generators","WriteBurst",{"type","string","size"},{},
+generators.WriteBurst = R.newGenerator("generators","WriteBurst",{"type","string","size","rate"},{},
 function(args)
   J.err( R.isHandshake(args.type), "WriteBurst: input must be handshaked")
   return SOC.writeBurst(args.string, args.size[1], args.size[2], R.extractData(args.type), 0)

diff --git a/src/types.lua b/src/types.lua
@@ -115,8 +115,8 @@ function types.tuple( list )
   err(J.keycount(list)==#list,"types.tuple: input table is not an array")
   err(#list>0, "no empty tuple types!")
 
-  for _,v in ipairs(list) do
-    err( types.isType(v), "types.tuple: all items in list must be types")
+  for k,v in ipairs(list) do
+    err( types.isType(v), "types.tuple: all items in list must be types, but item "..tostring(k).." is :"..tostring(v))
     err( types.isBasic(v), "types.tuple: input type must be basic, but is: "..tostring(v) )
     err(v:verilogBits()>0,"types.tuple: all types in list must have >0 bits")
   end

diff --git a/unittests/makefile b/unittests/makefile
@@ -80,7 +80,7 @@ $(BUILDDIR)/fwriteseq12.compiles.txt: fwriteseq12.lua
 
 $(BUILDDIR)/fwriteseq12.correct.txt: $(BUILDDIR)/verilogcorrect.txt
 	diff $(BUILDDIR)/fwriteseq16test.raw $(BUILDDIR)/dbg_terra_fwriteseq12.raw > $(BUILDDIR)/fwriteseq12test.diff
-	diff $(BUILDDIR)/fwriteseq16test.raw $(BUILDDIR)/dbg_verilator_fwriteseq12.raw > $(BUILDDIR)/fwriteseq12testVerilog.diff
+	diff $(BUILDDIR)/fwriteseq16test.raw $(BUILDDIR)/dbg_verilatorSOC_fwriteseq12.raw > $(BUILDDIR)/fwriteseq12testVerilog.diff
 	test ! -s $(BUILDDIR)/$*.fwriteseq12testVerilog.diff && touch $@
 ###################
 $(BUILDDIR)/fwriteseq18.compiles.txt: fwriteseq18.lua
@@ -89,7 +89,7 @@ $(BUILDDIR)/fwriteseq18.compiles.txt: fwriteseq18.lua
 	$(LUA) fwriteseq18.lua metadata
 
 $(BUILDDIR)/fwriteseq18.correct.txt: $(BUILDDIR)/verilogcorrect.txt
-	diff $(BUILDDIR)/dbg_terra_fwriteseq18.raw $(BUILDDIR)/dbg_verilator_fwriteseq18.raw > $(BUILDDIR)/fwriteseq18test.diff
+	diff $(BUILDDIR)/dbg_terra_fwriteseq18.raw $(BUILDDIR)/dbg_verilatorSOC_fwriteseq18.raw > $(BUILDDIR)/fwriteseq18test.diff
 	test ! -s $(BUILDDIR)/$*.fwriteseq18test.diff && touch $@
 ###################
 $(BUILDDIR)/fwriteseq24.compiles.txt: fwriteseq24.lua
@@ -98,9 +98,9 @@ $(BUILDDIR)/fwriteseq24.compiles.txt: fwriteseq24.lua
 	$(LUA) fwriteseq24.lua metadata
 
 $(BUILDDIR)/fwriteseq24.correct.txt: $(BUILDDIR)/verilogcorrect.txt
-	diff $(BUILDDIR)/dbg_terra_fwriteseq24.raw $(BUILDDIR)/dbg_verilator_fwriteseq24.raw > $(BUILDDIR)/fwriteseq24test.diff
+	diff $(BUILDDIR)/dbg_terra_fwriteseq24.raw $(BUILDDIR)/dbg_verilatorSOC_fwriteseq24.raw > $(BUILDDIR)/fwriteseq24test.diff
 	diff $(BUILDDIR)/fwriteseq24.terra.raw $(BUILDDIR)/dbg_terra_fwriteseq24.raw > $(BUILDDIR)/fwriteseq24test2.diff
-	diff $(BUILDDIR)/fwriteseq24.terra.raw $(BUILDDIR)/dbg_verilator_fwriteseq24.raw > $(BUILDDIR)/fwriteseq24testVerilog.diff
+	diff $(BUILDDIR)/fwriteseq24.terra.raw $(BUILDDIR)/dbg_verilatorSOC_fwriteseq24.raw > $(BUILDDIR)/fwriteseq24testVerilog.diff
 	test ! -s $(BUILDDIR)/$*.fwriteseq24test.diff && touch $@
 ###################
 $(BUILDDIR)/fwriteseq37.compiles.txt: fwriteseq37.lua
@@ -109,7 +109,7 @@ $(BUILDDIR)/fwriteseq37.compiles.txt: fwriteseq37.lua
 	$(LUA) fwriteseq37.lua metadata
 
 $(BUILDDIR)/fwriteseq37.correct.txt: $(BUILDDIR)/verilogcorrect.txt
-	diff $(BUILDDIR)/dbg_terra_fwriteseq37.raw $(BUILDDIR)/dbg_verilator_fwriteseq37.raw > $(BUILDDIR)/fwriteseq37test.diff
+	diff $(BUILDDIR)/dbg_terra_fwriteseq37.raw $(BUILDDIR)/dbg_verilatorSOC_fwriteseq37.raw > $(BUILDDIR)/fwriteseq37test.diff
 	test ! -s $(BUILDDIR)/$*.fwriteseq37test.diff && touch $@
 ###################