Merge branch 'master' of github.com:jamesjiang52/Bitwise

bitwise/gate/BUF.py

@@ -0,0 +1,33 @@
+"""
+The following classes are defined:
+    Buffer
+"""
+
+from .. import wire
+
+Wire = wire.Wire
+
+
+class Buffer:
+    """Construct a new Buffer.
+
+    Args:
+        input_1: An object of type Wire. The input to the buffer.
+        output: An object of type Wire. The output of the buffer.
+    """
+    def __init__(self, input_1, output):
+        self.input_1 = input_1
+        self.output = output
+
+        self.input_1._bind_to(self._update_input_1)
+
+        if self.input_1.value == 1:
+            self.output.value = 1
+        else:
+            self.output.value = 0
+
+    def _update_input_1(self, value):
+        if value == 1:
+            self.output.value = 1
+        else:
+            self.output.value = 0

bitwise/gate/__init__.py

@@ -1,4 +1,5 @@
 from .AND import *
+from .BUF import *
 from .NAND import *
 from .NOR import *
 from .NOT import *

bitwise/signal/PISO.py

@@ -0,0 +1,165 @@
+"""
+The following classes are defined:
+    ParallelToSerialConverter4To1
+    ParallelToSerialConverter8To1
+    ParallelToSerialConverter16To1
+"""
+
+from .. import wire
+from .. import storage
+
+Wire = wire.Wire
+Bus4 = wire.Bus4
+Bus8 = wire.Bus8
+Bus16 = wire.Bus16
+
+
+class ParallelToSerialConverter4To1:
+    """
+
+    """
+    def __init__(
+        self,
+        enable,
+        reset_n,
+        parallel_load_n,
+        data_bus,
+        clock,
+        output
+    ):
+        if len(data_bus.wires) != 4:
+            raise TypeError(
+                "Expected bus of width 4, received bus of width {0}.".format(
+                    len(data_bus.wires)
+                )
+            )
+
+        vcc = Wire()
+        vcc.value = 1
+        gnd = Wire()
+        gnd.value = 0
+
+        d = Wire()
+        b_1 = Wire()
+        b_2 = Wire()
+        b_3 = Wire()
+        b_4 = Wire()
+        b_bus = Bus4(b_1, b_2, b_3, b_4)
+
+        storage.ShiftRegister4(
+            enable,
+            reset_n,
+            parallel_load_n,
+            data_bus,
+            d,
+            clock,
+            b_bus,
+            output
+        )
+
+
+class ParallelToSerialConverter8To1:
+    """
+
+    """
+    def __init__(
+        self,
+        enable,
+        reset_n,
+        parallel_load_n,
+        data_bus,
+        clock,
+        output
+    ):
+        if len(data_bus.wires) != 8:
+            raise TypeError(
+                "Expected bus of width 8, received bus of width {0}.".format(
+                    len(data_bus.wires)
+                )
+            )
+
+        vcc = Wire()
+        vcc.value = 1
+        gnd = Wire()
+        gnd.value = 0
+
+        d = Wire()
+        b_1 = Wire()
+        b_2 = Wire()
+        b_3 = Wire()
+        b_4 = Wire()
+        b_5 = Wire()
+        b_6 = Wire()
+        b_7 = Wire()
+        b_8 = Wire()
+        b_bus = Bus8(b_1, b_2, b_3, b_4, b_5, b_6, b_7, b_8)
+
+        storage.ShiftRegister8(
+            enable,
+            reset_n,
+            parallel_load_n,
+            data_bus,
+            d,
+            clock,
+            b_bus,
+            output
+        )
+
+
+class ParallelToSerialConverter16To1:
+    """
+
+    """
+    def __init__(
+        self,
+        enable,
+        reset_n,
+        parallel_load_n,
+        data_bus,
+        clock,
+        output
+    ):
+        if len(data_bus.wires) != 16:
+            raise TypeError(
+                "Expected bus of width 16, received bus of width {0}.".format(
+                    len(data_bus.wires)
+                )
+            )
+
+        vcc = Wire()
+        vcc.value = 1
+        gnd = Wire()
+        gnd.value = 0
+
+        d = Wire()
+        b_1 = Wire()
+        b_2 = Wire()
+        b_3 = Wire()
+        b_4 = Wire()
+        b_5 = Wire()
+        b_6 = Wire()
+        b_7 = Wire()
+        b_8 = Wire()
+        b_9 = Wire()
+        b_10 = Wire()
+        b_11 = Wire()
+        b_12 = Wire()
+        b_13 = Wire()
+        b_14 = Wire()
+        b_15 = Wire()
+        b_16 = Wire()
+        b_bus = Bus16(
+            b_1, b_2, b_3, b_4, b_5, b_6, b_7, b_8,
+            b_9, b_10, b_11, b_12, b_13, b_14, b_15, b_16
+        )
+
+        storage.ShiftRegister16(
+            enable,
+            reset_n,
+            parallel_load_n,
+            data_bus,
+            d,
+            clock,
+            b_bus,
+            output
+        )

bitwise/signal/SIPO.py

@@ -0,0 +1,141 @@
+"""
+The following classes are defined:
+    SerialToParallelConverter1To4
+    SerialToParallelConverter1To8
+    SerialToParallelConverter1To16
+"""
+
+from .. import wire
+from .. import storage
+
+Wire = wire.Wire
+Bus4 = wire.Bus4
+Bus8 = wire.Bus8
+Bus16 = wire.Bus16
+
+
+class SerialToParallelConverter1To4:
+    """
+
+    """
+    def __init__(self, enable, reset_n, data, clock, output_bus):
+        if len(output_bus.wires) != 4:
+            raise TypeError(
+                "Expected bus of width 4, received bus of width {0}.".format(
+                    len(output_bus.wires)
+                )
+            )
+
+        vcc = Wire()
+        vcc.value = 1
+        gnd = Wire()
+        gnd.value = 0
+
+        d_1 = Wire()
+        d_2 = Wire()
+        d_3 = Wire()
+        d_4 = Wire()
+        b = Wire()
+        d_bus = Bus4(d_1, d_2, d_3, d_4)
+
+        storage.ShiftRegister4(
+            enable,
+            reset_n,
+            vcc,
+            d_bus,
+            data,
+            clock,
+            output_bus,
+            b
+        )
+
+
+class SerialToParallelConverter1To8:
+    """
+
+    """
+    def __init__(self, enable, reset_n, data, clock, output_bus):
+        if len(output_bus.wires) != 8:
+            raise TypeError(
+                "Expected bus of width 8, received bus of width {0}.".format(
+                    len(output_bus.wires)
+                )
+            )
+
+        vcc = Wire()
+        vcc.value = 1
+        gnd = Wire()
+        gnd.value = 0
+
+        d_1 = Wire()
+        d_2 = Wire()
+        d_3 = Wire()
+        d_4 = Wire()
+        d_5 = Wire()
+        d_6 = Wire()
+        d_7 = Wire()
+        d_8 = Wire()
+        b = Wire()
+        d_bus = Bus8(d_1, d_2, d_3, d_4, d_5, d_6, d_7, d_8)
+
+        storage.ShiftRegister8(
+            enable,
+            reset_n,
+            vcc,
+            d_bus,
+            data,
+            clock,
+            output_bus,
+            b
+        )
+
+
+class SerialToParallelConverter1To16:
+    """
+
+    """
+    def __init__(self, enable, reset_n, data, clock, output_bus):
+        if len(output_bus.wires) != 16:
+            raise TypeError(
+                "Expected bus of width 16, received bus of width {0}.".format(
+                    len(output_bus.wires)
+                )
+            )
+
+        vcc = Wire()
+        vcc.value = 1
+        gnd = Wire()
+        gnd.value = 0
+
+        d_1 = Wire()
+        d_2 = Wire()
+        d_3 = Wire()
+        d_4 = Wire()
+        d_5 = Wire()
+        d_6 = Wire()
+        d_7 = Wire()
+        d_8 = Wire()
+        d_9 = Wire()
+        d_10 = Wire()
+        d_11 = Wire()
+        d_12 = Wire()
+        d_13 = Wire()
+        d_14 = Wire()
+        d_15 = Wire()
+        d_16 = Wire()
+        b = Wire()
+        d_bus = Bus16(
+            d_1, d_2, d_3, d_4, d_5, d_6, d_7, d_8,
+            d_9, d_10, d_11, d_12, d_13, d_14, d_15, d_16
+        )
+
+        storage.ShiftRegister16(
+            enable,
+            reset_n,
+            vcc,
+            d_bus,
+            data,
+            clock,
+            output_bus,
+            b
+        )

bitwise/signal/__init__.py

@@ -3,4 +3,6 @@
 from .ENC import *
 from .MUX import *
 from .INV_CTRL import *
+from .PISO import *
+from .SIPO import *
 from .SSD import *