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Liveness: improve for register allocation #469

Merged
merged 2 commits into from
Jun 5, 2023
Merged

Liveness: improve for register allocation #469

merged 2 commits into from
Jun 5, 2023

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vbgl
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@vbgl vbgl commented Jun 1, 2023

Fixes #455

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eponier commented Jun 1, 2023

I don't get the idea of the second commit. I have the impression that we are less precise than before, and it gives better results?

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vbgl commented Jun 1, 2023

Yes, I don’t really understand why we had this special case…

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vbgl commented Jun 1, 2023

Without this change, when there is x = y; with y live afterwards and x dead, we tell the register allocation that it is OK to allocate both x and y to the same register. Unfortunately, the checker does not know about the semantics of move instructions.

Maybe I could fix that instead…

@vbgl vbgl marked this pull request as draft June 1, 2023 13:50
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vbgl commented Jun 1, 2023

With this patch, the compiler would generate a dead mov, e.g., movq %rdi, %rax. Without this patch but with an improved checker, we would generate a silly dead mov, e.g., movq %rdi, %rdi.

Maybe it’s better to just crash…

@vbgl vbgl marked this pull request as ready for review June 1, 2023 15:31
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vbgl commented Jun 1, 2023

I think this change is good: it simplifies code that is unnecessarily complex.

let asmOp = Arch_extra.asm_opI X86_arch_full.X86_core.asm_e in
FSPa.fs_pa_make asmOp is_move_op PW.main
FSPa.fs_pa_make asmOp PW.main

(* We compute the reflexive and transitive clojure of dp *)
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Not so frequent that I am able to find a typo in a comment (clojure -> closure) :-)

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Fixed!

vbgl and others added 2 commits June 5, 2023 08:48
This somehow reverts commit 72d20a6

Co-authored-by: Benjamin Grēgoire <Benjamin.Gregoire@inria.fr>
@vbgl vbgl merged commit 7896310 into main Jun 5, 2023
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@vbgl vbgl deleted the fix-455 branch June 5, 2023 07:51
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Register allocation bug with instrinsics
3 participants