Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. It is also used in the verification of analog circuits and mixed-signal circuits, as well as in the design of genetic circuits.
Programs are implemented using Xilinx ISE Simulator.
- Full Adder Circuit
- 4-bit Counter
- 4-to-1 MUX
- 2-to-4 Decoder
- ALU (Arithmetic and Logic Unit)
- Division