Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
db		db
greybox_tmp		greybox_tmp
incremental_db/compiled_partitions		incremental_db/compiled_partitions
qdb/_compiler/signalgenerate/_flat/18.1.0/legacy/1		qdb/_compiler/signalgenerate/_flat/18.1.0/legacy/1
ASYNC_SHIFTIN.vhd		ASYNC_SHIFTIN.vhd
ASYNC_SHIFTOUT.vhd		ASYNC_SHIFTOUT.vhd
AsyncReceiver.vhd		AsyncReceiver.vhd
AsyncSender.vhd		AsyncSender.vhd
DIV.vhd		DIV.vhd
DIV2.vhd		DIV2.vhd
MasterSyncSerial.vhd		MasterSyncSerial.vhd
PLL_80.bsf		PLL_80.bsf
PLL_80.cmp		PLL_80.cmp
PLL_80.inc		PLL_80.inc
PLL_80.ppf		PLL_80.ppf
PLL_80.qip		PLL_80.qip
PLL_80.vhd		PLL_80.vhd
PLL_80_inst.vhd		PLL_80_inst.vhd
PulseReceiver.vhd		PulseReceiver.vhd
PulseTransmitter.vhd		PulseTransmitter.vhd
PulseTransmitter3.vhd		PulseTransmitter3.vhd
README.md		README.md
RECV_CTRL.vhd		RECV_CTRL.vhd
SEND_CTRL.vhd		SEND_CTRL.vhd
SlaveSyncSerial.vhd		SlaveSyncSerial.vhd
SpiComponent.vhd		SpiComponent.vhd
SpiMaster.vhd		SpiMaster.vhd
SpiReceiver.vhd		SpiReceiver.vhd
SpiSender.vhd		SpiSender.vhd
SyncSerialComponent.vhd		SyncSerialComponent.vhd
Type.vhd		Type.vhd
define.vhd		define.vhd
out_directory_tmp.txt.tmp		out_directory_tmp.txt.tmp
serv_req_info.txt		serv_req_info.txt
signalgenerate.asm.rpt		signalgenerate.asm.rpt
signalgenerate.cdf		signalgenerate.cdf
signalgenerate.done		signalgenerate.done
signalgenerate.fit.rpt		signalgenerate.fit.rpt
signalgenerate.fit.smsg		signalgenerate.fit.smsg
signalgenerate.fit.summary		signalgenerate.fit.summary
signalgenerate.flow.rpt		signalgenerate.flow.rpt
signalgenerate.jdi		signalgenerate.jdi
signalgenerate.map.rpt		signalgenerate.map.rpt
signalgenerate.map.summary		signalgenerate.map.summary
signalgenerate.merge.rpt		signalgenerate.merge.rpt
signalgenerate.merge.summary		signalgenerate.merge.summary
signalgenerate.out.sdc		signalgenerate.out.sdc
signalgenerate.pin		signalgenerate.pin
signalgenerate.pof		signalgenerate.pof
signalgenerate.qpf		signalgenerate.qpf
signalgenerate.qsf		signalgenerate.qsf
signalgenerate.qws		signalgenerate.qws
signalgenerate.restore.rpt		signalgenerate.restore.rpt
signalgenerate.sdc		signalgenerate.sdc
signalgenerate.sof		signalgenerate.sof
signalgenerate.sta.rpt		signalgenerate.sta.rpt
signalgenerate.sta.summary		signalgenerate.sta.summary
signalgenerate.vhd		signalgenerate.vhd
signalgenerate.vhdPreview		signalgenerate.vhdPreview
signalgenerate_assignment_defaults.qdf		signalgenerate_assignment_defaults.qdf
signalgenerate_description.txt		signalgenerate_description.txt

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pci_logic

实现了PCI DMA读写，PIO逻辑
支持32位
速率实测可达到111MB/s
顶层代码实现在signalgenerate.vhd中，其他文件是一些其他的接口文件

jbl19860422/pci_logic

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pci_logic

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