hardware: fix bug with itlbinsert

On insert, the ASID was taken from the next thread to be fetched, not from the one that executed the itlbinsert.
jbush001 · Jul 21, 2016 · c32f6c0 · c32f6c0
1 parent 6afa379
commit c32f6c0
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Showing 3 changed files with 5 additions and 1 deletion.
diff --git a/hardware/core/core.sv b/hardware/core/core.sv
@@ -109,6 +109,7 @@ module core
     logic               dt_instruction_valid;   // From dcache_tag_stage of dcache_tag_stage.v
     logic               dt_invalidate_tlb_all_en;// From dcache_tag_stage of dcache_tag_stage.v
     logic               dt_invalidate_tlb_en;   // From dcache_tag_stage of dcache_tag_stage.v
+    logic [`ASID_WIDTH-1:0] dt_itlb_update_asid;// From dcache_tag_stage of dcache_tag_stage.v
     page_index_t        dt_itlb_vpage_idx;      // From dcache_tag_stage of dcache_tag_stage.v
     vector_lane_mask_t  dt_mask_value;          // From dcache_tag_stage of dcache_tag_stage.v
     l1d_addr_t          dt_request_paddr;       // From dcache_tag_stage of dcache_tag_stage.v

diff --git a/hardware/core/dcache_tag_stage.sv b/hardware/core/dcache_tag_stage.sv
@@ -71,6 +71,7 @@ module dcache_tag_stage
     output                                      dt_invalidate_tlb_en,
     output                                      dt_invalidate_tlb_all_en,
     output page_index_t                         dt_itlb_vpage_idx,
+    output [`ASID_WIDTH - 1:0]                  dt_itlb_update_asid,
     output                                      dt_update_itlb_en,
     output page_index_t                         dt_update_itlb_ppage_idx,
     output                                      dt_update_itlb_present,
@@ -153,6 +154,7 @@ module dcache_tag_stage
     assign dt_itlb_vpage_idx = of_operand1[0][31-:`PAGE_NUM_BITS];
     assign dt_update_itlb_ppage_idx = new_tlb_value.ppage_idx;
     assign dt_update_itlb_executable = new_tlb_value.executable;
+    assign dt_itlb_update_asid = cr_current_asid[of_thread_idx];
 
     initial
     begin

diff --git a/hardware/core/ifetch_tag_stage.sv b/hardware/core/ifetch_tag_stage.sv
@@ -69,6 +69,7 @@ module ifetch_tag_stage
     // From dcache_tag_stage
     input                               dt_invalidate_tlb_en,
     input                               dt_invalidate_tlb_all_en,
+    input [`ASID_WIDTH - 1:0]           dt_itlb_update_asid,
     input page_index_t                  dt_itlb_vpage_idx,
     input                               dt_update_itlb_en,
     input                               dt_update_itlb_supervisor,
@@ -213,7 +214,7 @@ module ifetch_tag_stage
         .invalidate_en(dt_invalidate_tlb_en),
         .invalidate_all_en(dt_invalidate_tlb_all_en),
         .request_vpage_idx(cache_fetch_en ? pc_to_fetch[31-:`PAGE_NUM_BITS] : dt_itlb_vpage_idx),
-        .request_asid(cr_current_asid[selected_thread_idx]),
+        .request_asid(cache_fetch_en ? cr_current_asid[selected_thread_idx] : dt_itlb_update_asid),
         .update_ppage_idx(dt_update_itlb_ppage_idx),
         .lookup_ppage_idx(tlb_ppage_idx),
         .lookup_hit(tlb_hit),