Virtua Racing catridge pinouts and layout

IC 1 - SVP

This information is based on following the different traces in the chip from a "clean" board (a cart with all components removed).

Side A (bottom)

SVP Pin	Description	I/O	Connected to	Target pin
1	CART addr 20	Input	Cart port	B8
2	CART addr 13	Input	Cart port	A8
3	CART addr 21	Input	Cart port	B9
4	CART addr 5	Input	Cart port	A9
5	CART addr 22	Input	Cart port	B10
6	CART addr 14	Input	Cart port	A10
7	CART addr 23	Input	Cart port	B11
8	CART addr 4	Input	Cart port	A11
9	CART addr 15	Input	Cart port	A12
10	CART addr 3	Input	Cart port	A13
11	MD HSync/MHS	Input	Cart port	B14
12	CART addr 16	Input	Cart port	A14
13	5V	Input	PCB Plane	Pin 151 / C8
14	GND	Input	PCB Plane
15	GND	Input	PCB Plane
16	CART addr 2	Input	Cart port	A15
17	CART CAS0	Input	Cart port	B16
18	CART addr 17	Input	Cart port	A16
19	CART CE0	Input	Cart port	B17
20	CART addr 1	Input	Cart port	A17
21	CART AS latch	Input	IC5/AND	through IC5/6
22	M68K CLK inverted	Input	IC4/NOT	through IC4/6
23	GND	Input	PCB Plane	C7 / Cart A18
24	5V	Input	PCB Plane	C7 / Cart A31
25	5V	Input	PCB Plane	C7 / Cart A31
26	CART data 7	I/O	Cart port	A19
27	CART data 0	I/O	Cart port	A20
28	CART DTAK	Output	Cart port	B20
29	CART data 8	I/O	Cart port	A21
30	CART data 6	I/O	Cart port	A22
31	CART data 15	I/O	Cart port	B22
32	CART data 1	I/O	Cart port	A23
33	CART data 14	I/O	Cart port	B23
34	CART data 9	I/O	Cart port	A24
35	CART data 13	I/O	Cart port	B24
36	CART data 5	I/O	Cart port	A25
37	CART data 12	I/O	Cart port	B25
38	CART data 2	I/O	Cart port	A26
39	CART ASEL latch	Input	IC5/AND	through IC5/8
40	CART data 10	I/O	Cart port	A27

Side B (right)

SVP Pin	Description	I/O	Connected to	Target pin
41	VRES	Input	Cart port	B27
42	CART data 4	Input	Cart port	A28
43	CART LWR	Input	Cart port	B28
44	CART data 3	Input	Cart port	A29
45	5V	Input	C4
46	GND	Input	C4
47	CART data 11	Output	Cart port	A30
48	ROM addr 18	Output	IC2 / ROM	2
49	ROM addr 19	Output	IC2 / ROM	43
50	ROM addr 17	Output	IC2 / ROM	3
51	ROM addr 8	Output	IC2 / ROM	42
52	ROM addr 7	Output	IC2 / ROM	4
53	ROM addr 9	Output	IC2 / ROM	41
54	ROM addr 6	Output	IC2 / ROM	5
55	ROM addr 10	Output	IC2 / ROM	40
56	ROM addr 5	Output	IC2 / ROM	6
57	GND	Input	PCB Plane
58	GND	Input	PCB Plane
59	ROM addr 11	Output	IC2 / ROM	39
60	ROM addr 4	Output	IC2 / ROM	7
61	ROM addr 12	Output	IC2 / ROM	38
62	ROM addr 3	Output	IC2 / ROM	8
63	ROM addr 13	Output	IC2 / ROM	37
64	ROM addr 2	Output	IC2 / ROM	9
65	ROM addr 14	Output	IC2 / ROM	36
66	ROM addr 1	Output	IC2 / ROM	10
67	ROM addr 15	Output	IC2 / ROM	35
68	GND	Input	PCB Plane
69	ROM addr 0	Output	IC2 / ROM	11
70	ROM addr 16	Output	IC2 / ROM	34
71	ROM #CE	Output	IC2 / ROM	12
72	Not connected	N/A
73	ROM #OE	Output	IC2 / ROM	14
74	Not connected	N/A
75	Not connected	N/A
76	ROM data 15	Input	IC2 / ROM	31
77	ROM data 0	Input	IC2 / ROM	15
78	ROM data 7	Input	IC2 / ROM	30
79	ROM data 9	Input	IC2 / ROM	16
80	GND	Input	PCB Plane

Fun detail: apparently the SVP chip has the ability to put the catridge in Master System mode through pin 47.

Side C (up)

SVP Pin	Description	I/O	Connected to	Target pin
81	5V	Input	C11
82	ROM data 14	Input	IC2 / ROM	29
83	ROM data 1	Input	IC2 / ROM	17
84	ROM data 6	Input	IC2 / ROM	28
85	ROM data 9	Input	IC2 / ROM	18
86	ROM data 13	Input	IC2 / ROM	27
87	ROM data 2	Input	IC2 / ROM	19
88	ROM data 5	Input	IC2 / ROM	26
89	ROM data 10	Input	IC2 / ROM	20
90	ROM data 12	Input	IC2 / ROM	25
91	ROM data 3	Input	IC2 / ROM	21
92	ROM data 3	Input	IC2 / ROM	21
93	5V	Input	PCB plane
94	5V	Input	PCB plane
95	GND	Input	PCB plane
96	GND	Input	PCB plane
97	ROM data 4	Input	IC2 / ROM	24
98	ROM data 11	Input	IC2 / ROM	22
99	Not connected	N/A
100	GND	Input	PCB plane
101	PLL #1	?????	R3
102	5V	Input	PCB plane
103	PLL #2	?????	R2
104	PLL #3	?????	C12
105	PLL #4	?????	C12
106	PLL #5	?????	R1
107	GND	Input	PCB plane
108	GND	Input	PCB plane
109	5V	Input	PCB plane
110	GND	Input	PCB plane
111	GND	Input	PCB plane
112	GND	Input	PCB plane
113	GND	Input	PCB plane
114	GND	Input	PCB plane
115	GND	Input	PCB plane
116	GND	Input	PCB plane
117	GND	Input	PCB plane
118	RAM addr 0	Output	IC3 / RAM	14
119	RAM #CAS	Output	IC3 / RAM	29
120	5V	Input	PCB plane

PLL pins on the middle of this side are still unknown how they work. The result of the PLL seems to be the output of C12 (connected to either pin 104 or 105).

Side D (left)

SVP Pin	Description	I/O	Connected to	Target pin
121	GND	Input	C16/C10
122	RAM #LW	Output	IC3 / RAM	13
123	RAM #OE	Output	IC3 / RAM	28
124	Not connected	N/A
125	RAM A7 / I/O 8	I/O	IC3 / RAM	9 / 24
126	RAM I/O 9	I/O	IC3 / RAM	32
127	RAM A6 / I/O 7	I/O	IC3 / RAM	8 / 23
128	RAM I/O 10	I/O	IC3 / RAM	33
129	RAM A5 / I/O 6	I/O	IC3 / RAM	7 / 22
130	RAM I/O 11	I/O	IC3 / RAM	34
131	RAM A4 / I/O 5	I/O	IC3 / RAM	6 / 19
132	RAM I/O 12	I/O	IC3 / RAM	35
133	RAM A3 / I/O 4	I/O	IC3 / RAM	5 / 18
134	RAM I/O 13	I/O	IC3 / RAM	36
135	RAM A2 / I/O 3	I/O	IC3 / RAM	4 / 17
136	RAM I/O 14	I/O	IC3 / RAM	37
137	GND	Input	PCB plane
138	GND	Input	PCB plane
139	5V	Input	Pin 144/C15
140	RAM A1 / I/O 2	I/O	IC3 / RAM	3 / 16
141	RAM I/O 15	I/O	IC3 / RAM	38
142	RAM A0 / I/O 1	I/O	IC3 / RAM	2 / 15
143	RAM I/O 16	I/O	IC3 / RAM	39
144	5V	Input	Pin 139/C15
145	GND	Input	C19
146	Not connected	N/A
147	Not connected	N/A
148	Not connected	N/A
149	Not connected	N/A
150	Not connected	N/A
151	5V	Input	C19
152	CART addr 8	I/O	Cart port	A3
153	CART addr 9	Input	Cart port	B4
154	CART addr 11	I/O	Cart port	A4
155	CART addr 10	Input	Cart port	B5
156	CART addr 7	I/O	Cart port	A5
157	CART addr 18	Input	Cart port	B6
158	CART addr 12	I/O	Cart port	A6
159	CART addr 19	Input	Cart port	B7
160	CART addr 6	I/O	Cart port	A7

Note: Half of the RAM chip's data and address lines (I/O 1-8, addr 0-7) are connected in pairs to the same pins in SVP, probably as a pin/trace space saving method.

IC2 / Fast ROM chip (27C322-compatible)

IC Pin	Description	I/O	Connected to	Target pin
1	Not connected	N/A
2	ROM addr 18	Input	IC1/SVP	48
3	ROM addr 17	Input	IC1/SVP	50
4	ROM addr 7	Input	IC1/SVP	52
5	ROM addr 6	Input	IC1/SVP	54
6	ROM addr 5	Input	IC1/SVP	56
7	ROM addr 4	Input	IC1/SVP	60
8	ROM addr 3	Input	IC1/SVP	62
9	ROM addr 2	Input	IC1/SVP	64
10	ROM addr 1	Input	IC1/SVP	66
11	ROM addr 0	Input	IC1/SVP	69
12	CE#	Input	IC1/SVP	71
13	GND	Input
14	OE#	Input	IC1/SVP	73
15	ROM data 0	I/O	IC1/SVP	77
16	ROM data 8	I/O	IC1/SVP	79
17	ROM data 1	I/O	IC1/SVP	83
18	ROM data 9	I/O	IC1/SVP	85
19	ROM data 2	I/O	IC1/SVP	87
20	ROM data 10	I/O	IC1/SVP	89
21	ROM data 3	I/O	IC1/SVP	91
22	ROM data 11	I/O	IC1/SVP	97
23	5V	Input
24	CART data 4	I/O	IC1/SVP	96
25	CART data 12	I/O	IC1/SVP	90
26	CART data 5	I/O	IC1/SVP	88
27	CART data 13	I/O	IC1/SVP	86
28	CART data 6	I/O	IC1/SVP	84
29	CART data 14	I/O	IC1/SVP	82
30	CART data 7	I/O	IC1/SVP	78
31	CART data 15	I/O	IC1/SVP	76
32	GND	Input
33	BYTE#	Input	VCC Plane
34	ROM addr 16	Input	IC1/SVP	70
35	ROM addr 15	Input	IC1/SVP	67
36	ROM addr 14	Input	IC1/SVP	65
37	ROM addr 13	Input	IC1/SVP	63
38	ROM addr 12	Input	IC1/SVP	61
39	ROM addr 11	Input	IC1/SVP	59
40	ROM addr 10	Input	IC1/SVP	55
41	ROM addr 9	Input	IC1/SVP	53
42	ROM addr 8	Input	IC1/SVP	51
43	ROM addr 19	Input	IC1/SVP	49
44	ROM addr 20	Input	N/C

IC3 / TC511664BJ-80 (128KB RAM)

IC Pin	Description	I/O	Connected to	Target pin
1	5V	Input	C15
2	RAM I/O 1	I/O	IC1/SVP	142
3	RAM I/O 2	I/O	IC1/SVP	140
4	RAM I/O 3	I/O	IC1/SVP	135
5	RAM I/O 4	I/O	IC1/SVP	133
6	RAM I/O 5	I/O	IC1/SVP	131
7	RAM I/O 6	I/O	IC1/SVP	129
8	RAM I/O 7	I/O	IC1/SVP	127
9	RAM I/O 8	I/O	IC1/SVP	125
10	Not connected	N/A
11	5V	Input	C16
12	RAM UW#	Input		122
13	RAM LW#	Input	IC1/SVP	122
14	RAM RAS#	Input	IC1/SVP	118
15	RAM addr 0	Input	IC1/SVP	142
16	RAM addr 1	Input	IC1/SVP	140
17	RAM addr 2	Input	IC1/SVP	135
18	RAM addr 3	Input	IC1/SVP	133
19	RAM addr 4	Input	IC1/SVP	131
20	5V	Input	C17
21	GND	Input	PCB Plane
22	RAM addr 5	Input	IC1/SVP	129
23	RAM addr 6	Input	IC1/SVP	127
24	RAM addr 7	Input	IC1/SVP	125
25	Not connected	N/A
26	Not connected	N/A
27	Not connected	N/A
28	RAM OE#	Input	IC1/SVP	123
29	RAM CAS#	Input	IC1/SVP	119
30	GND	Input	PCB Plane
31	Not connected	N/A
32	RAM I/O 9	I/O	IC1/SVP	126
33	RAM I/O 10	I/O	IC1/SVP	128
34	RAM I/O 11	I/O	IC1/SVP	130
35	RAM I/O 12	I/O	IC1/SVP	132
36	RAM I/O 13	I/O	IC1/SVP	134
37	RAM I/O 14	I/O	IC1/SVP	136
38	RAM I/O 15	I/O	IC1/SVP	141
39	RAM I/O 16	I/O	IC1/SVP	143
40	GND	Input	PCB Plane

IC4/HCT04

Inverter gate array (https://pdf1.alldatasheet.com/datasheet-pdf/view/46178/SLS/HCT04.html)

IC Pin	Description	I/O	Connected to	Target pin
1	A1 / M68K CLK	Input	Cart port	CART B19
2	Y1 / #M68K CLK	Output	IC4	3
3	A2 / #M68K CLK	Input	IC4
4	Y2 / M68K CLK	Output	IC4	5
5	A3 / M68K CLK	Input	IC4
6	Y3 / #M68K CLK	Output	SVP	22
7	GND	Input	PCB plane
8	Y4	Output
9	A4 / GND	Input
10	Y5	Output
11	A5 / GND	Input
12	Y6	Output
13	A6 / GND	Input
14	VCC	Input	PCB Plane

Half of the IC is used to delay the M68K clock signal coming from the cart (going through 3 inversions and capacitor C19 all the way to the RC circuit on the top, feeding the clock pins in the SVP) finally reaching SVP pin 22 (inverted). It's probably inverted to allow interleaved reads on the external ROM by both the Mega Drive and the SVP, without needing a complicated arbitration mechanism. The outputs in the other half of the IC are unused.

IC5/HCT08

AND gate array (https://pdf1.alldatasheet.com/datasheet-pdf/view/27977/TI/HCT08.html)

IC Pin	Description	I/O	Connected to	Target pin
1	1A / 5V	Input	PCB Plane
2	1B / CART AS	Input	Cart port	B18
3	1Y	Output	R4
4	2A	Input	R4
5	2B / CART AS	Input	Cart port	B18
6	2Y	Output	SVP	21
7	GND	Input	PCB plane
8	3Y	Output	SVP	39
9	3A / CART ASEL	Input	Cart port	B26
10	3B	Input	R5
11	4Y	Output	R5
12	4A / CART ASEL	Input	Cart port	B26
13	4B / VCC	Input	PCB Plane
14	VCC	Input	PCB Plane

This IC seems to be basically latching on AS and ASEL signals from the cartridge port, relaying them to SVP pins 21 (for AS) and 39 (for ASEL). In both cases signals are successfully AND'ed with an input of 5V twice (through a net of R4/C3 or R5/C4 for each of the signals).