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examples: Make frequency a parameter
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Jean THOMAS committed Aug 6, 2020
1 parent 5b248f9 commit 3944f60
Showing 1 changed file with 6 additions and 4 deletions.
10 changes: 6 additions & 4 deletions examples/soc.py
Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,8 @@ def __init__(self, *,
self._decoder = wishbone.Decoder(addr_width=30, data_width=32, granularity=8,
features={"cti", "bte"})

freq = 100e6

self.crg = ECPIX5CRG()

self.cpu = MinervaCPU(reset_address=0)
Expand All @@ -48,28 +50,28 @@ def __init__(self, *,
self.ram = SRAMPeripheral(size=4096)
self._decoder.add(self.ram.bus, addr=0x1000)

self.uart = AsyncSerialPeripheral(divisor=100000000//115200, pins=uart_pins)
self.uart = AsyncSerialPeripheral(divisor=int(freq//115200), pins=uart_pins)
self._decoder.add(self.uart.bus, addr=0x2000)


self.ddrphy = DomainRenamer("dramsync")(ECP5DDRPHY(ddr_pins))
self._decoder.add(self.ddrphy.bus, addr=ddrphy_addr)

ddrmodule = MT41K256M16(platform.default_clk_frequency, "1:2")
ddrmodule = MT41K256M16(freq, "1:2")

self.dramcore = DomainRenamer("dramsync")(gramCore(
phy=self.ddrphy,
geom_settings=ddrmodule.geom_settings,
timing_settings=ddrmodule.timing_settings,
clk_freq=platform.default_clk_frequency))
clk_freq=freq))
self._decoder.add(self.dramcore.bus, addr=dramcore_addr)

self.drambone = DomainRenamer("dramsync")(gramWishbone(self.dramcore))
self._decoder.add(self.drambone.bus, addr=ddr_addr)

self.memory_map = self._decoder.bus.memory_map

self.clk_freq = platform.default_clk_frequency
self.clk_freq = freq

def elaborate(self, platform):
m = Module()
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