Update code around "reset vector":

* remove hardcoded PC * Redirect $fff0-$ffff to $bff0-$bffe in SAM * update SBC, too. * remove old "bus area" stuff * see also: http://archive.worldofdragon.org/phpBB3/viewtopic.php?f=5&t=4911
jedie · Aug 6, 2014 · 70fa59d · 70fa59d
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commit 70fa59d
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Showing 13 changed files with 29 additions and 91 deletions.
diff --git a/dragonpy/CoCo/periphery_coco.py b/dragonpy/CoCo/periphery_coco.py
@@ -43,13 +43,6 @@ def write_word_info(self, cpu_cycles, op_address, address, value):
         log.critical("%04x| write word $%04x to $%04x ?!?!" % (
             op_address, value, address
         ))
-
-    def reset_vector(self, cpu_cycles, op_address, address):
-#         ea = 0x8C1B
-        ea = 0xA027
-#         ea = 0xC000
-        log.info("%04x| %04x        [RESET]" % (address, ea))
-        return ea # FIXME: RESET interrupt service routine ???
 
 
 def test_run_direct():

diff --git a/dragonpy/Dragon32/MC6883_SAM.py b/dragonpy/Dragon32/MC6883_SAM.py
@@ -84,6 +84,16 @@ def __init__(self, cfg, memory):
         #  Dragon 64 only:
         self.memory.add_write_byte_callback(self.write_D64_dynamic_memory, 0xffc9)
 
+        self.memory.add_read_byte_callback(self.interrupt_vectors, 0xfff0, 0xffff)
+
+    def interrupt_vectors(self, cpu_cycles, op_address, address):
+        new_address = address-0x4000
+        value = self.memory.read_byte(new_address)
+        log.critical("read interrupt vector $%04x redirect in SAM to $%04x use value $%02x",
+            address, new_address, value
+        )
+        return value
+
 #     def read_VDG_mode_register_v0(self, cpu_cycles, op_address, address):
 #         log.error("TODO: read VDG mode register V0 $%04x", address)
 #         return 0x00

diff --git a/dragonpy/Dragon32/config.py b/dragonpy/Dragon32/config.py
@@ -44,23 +44,6 @@ class Dragon32Cfg(BaseConfig):
     ROM_END = 0xBFFF
     ROM_SIZE = 0x4000 # 16384 Bytes
 
-#     RESET_VECTOR = 0xB3B4 # RESET interrupt service routine (CoCo $a027)
-#     RESET_VECTOR = 0xB3BA # Cold start routine - clears lo mem, inits BASIC
-#     RESET_VECTOR = 0xB39B # Called after Hardware init routine, following a RESET Inits stack, checks for Cold/warm start
-    RESET_VECTOR = 0xFFFE # RESET     ($b3b4; D64 64K mode $c000 - never accessed)
-#     RESET_VECTOR = 0xFFFC
-
-    BUS_ADDR_AREAS = (
-        # TODO: Add all devices!
-        (0x0400, 0x05ff, "Alphanumeric Display"),
-        (0xc000, 0xfeff, "DOS ROM / cartridge expansion port"),
-        (0xff00, 0xff04, "PIA 0 (Peripheral Interface Adaptor MC6821)"),
-        (0xff04, 0xff07, "D64 ACIA serial port"),
-        (0xff20, 0xff23, "PIA 1 (Peripheral Interface Adaptor MC6821)"),
-        (0xffc0, 0xffdf, "SAM (Synchronous Address Multiplexer MC6883)"),
-        (0xfff0, 0xfffe, "Interrupt vectors"),
-    )
-
     DEFAULT_ROM = os.path.join(
         os.path.abspath(os.path.dirname(__file__)),
         "d32.rom"

diff --git a/dragonpy/Dragon32/periphery_dragon.py b/dragonpy/Dragon32/periphery_dragon.py
@@ -44,40 +44,15 @@ def __init__(self, cfg, memory):
         self.sam = SAM(cfg, memory)
         self.pia = PIA(cfg, memory)
 
-#         map_address_range(
-#             self.read_byte_func_map,
-#             # $c000-$feff ; Available address range to cartridge expansion port 32K mode
-#             start_addr=0xC000, end_addr=0xfeff,
-#             callback_func=self.no_dos_rom
-#         )
-
-
         self.memory.add_read_byte_callback(self.no_dos_rom, 0xC000)
-        self.memory.add_read_byte_callback(self.reset_vector, 0xfffe)
-
         self.memory.add_read_word_callback(self.no_dos_rom, 0xC000)
-        self.memory.add_read_word_callback(self.reset_vector, 0xfffe)
-
-#         self.read_byte_func_map.update({
-#             0xc000: self.no_dos_rom,
-#             0xfffe: ,
-#         })
-#         self.read_word_func_map.update({
-#             0xc000: self.no_dos_rom,
-#             0xfffe: self.reset_vector,
-#         })
 
         self.running = True
 
     def no_dos_rom(self, cpu_cycles, op_address, address):
         log.error("%04x| TODO: DOS ROM requested. Send 0x00 back", op_address)
         return 0x00
 
-    def reset_vector(self, cpu_cycles, op_address, address):
-        ea = 0xb3b4
-        log.info("%04x| %04x        [RESET]" % (address, ea))
-        return ea # FIXME: RESET interrupt service routine ???
-
     def update(self, cpu_cycles):
 #        log.critical("update pygame")
         if not self.running:

diff --git a/dragonpy/Multicomp6809/config.py b/dragonpy/Multicomp6809/config.py
@@ -39,8 +39,6 @@ class Multicomp6809Cfg(BaseConfig):
 #     ROM_END = 0xBFFF
 #     ROM_SIZE = 0x2000 # 8192 Bytes
 
-    RESET_VECTOR = 0xBFFE
-
     BUS_ADDR_AREAS = (
         (0xFFD8, 0xFFDF, "SD Card"),
         (0xFFD2, 0xFFD3, "Interface 2"),

diff --git a/dragonpy/Multicomp6809/periphery_Multicomp6809.py b/dragonpy/Multicomp6809/periphery_Multicomp6809.py
@@ -39,19 +39,11 @@ def __init__(self, cfg):
 #         (0xFFD0, 0xFFD1, "Interface 1 (serial interface or TV/Keyboard)"),
 #         (0xBFF0, 0xBFFF, "Interrupt vectors"),
 #     )
-
-        self.read_byte_func_map = {
-            0xFFD0: self.read_acia_status, # Control/status port of ACIA
-            0xFFD1: self.read_acia_data, # Data port of ACIA
-            0xbffe: self.reset_vector,
-        }
-        self.write_byte_func_map = {
-            0xFFD0: self.write_acia_status, # Control/status port of ACIA
-            0xFFD1: self.write_acia_data, # Data port of ACIA
-        }
-
-    def reset_vector(self, cpu_cycles, op_address, address):
-        return self.cfg.ROM_START + 0x0046
+        self.memory.add_read_byte_callback(self.read_acia_status, 0xffd0) #  Control/status port of ACIA
+        self.memory.add_read_byte_callback(self.read_acia_data, 0xffd1) #  Data port of ACIA
+
+        self.memory.add_write_byte_callback(self.write_acia_status, 0xffd0) #  Control/status port of ACIA
+        self.memory.add_write_byte_callback(self.write_acia_data, 0xffd1) #  Data port of ACIA
 
     def write_acia_status(self, cpu_cycles, op_address, address, value):
         return 0xff

diff --git a/dragonpy/Simple6809/periphery_simple6809.py b/dragonpy/Simple6809/periphery_simple6809.py
@@ -40,8 +40,6 @@ def __init__(self, cfg, memory):
         self.memory.add_read_byte_callback(self.read_acia_status, 0xa000) #  Control/status port of ACIA
         self.memory.add_read_byte_callback(self.read_acia_data, 0xa001) #  Data port of ACIA
 
-        self.memory.add_read_word_callback(self.reset_vector, 0xbffe)
-
         self.memory.add_write_byte_callback(self.write_acia_status, 0xa000) #  Control/status port of ACIA
         self.memory.add_write_byte_callback(self.write_acia_data, 0xa001) #  Data port of ACIA
 

diff --git a/dragonpy/components/cpu6809.py b/dragonpy/components/cpu6809.py
@@ -64,7 +64,8 @@ def decorator(func):
 
 
 class CPU(object):
-
+    RESET_VECTOR = 0xfffe
+
     def __init__(self, memory, cfg):
         self.memory = memory
         self.cfg = cfg
@@ -84,7 +85,7 @@ def __init__(self, memory, cfg):
         self.system_stack_pointer = ValueStorage16Bit(REG_S, 0)
 
         # PC - 16 bit program counter register
-        self.program_counter = ValueStorage16Bit(REG_PC, self.cfg.RESET_VECTOR)
+        self.program_counter = ValueStorage16Bit(REG_PC, 0)
 
         self.accu_a = ValueStorage8Bit(REG_A, 0) # A - 8 bit accumulator
         self.accu_b = ValueStorage8Bit(REG_B, 0) # B - 8 bit accumulator
@@ -228,7 +229,7 @@ def reset(self):
 #         self.program_counter = self.cfg.RESET_VECTOR
 
 #        log.info("\tread word from $%x" % self.cfg.RESET_VECTOR)
-        ea = self.memory.read_word(self.cfg.RESET_VECTOR)
+        ea = self.memory.read_word(self.RESET_VECTOR)
 #        log.info("\tset PC to $%x" % (ea))
         self.program_counter.set(ea)
 

diff --git a/dragonpy/components/periphery.py b/dragonpy/components/periphery.py
@@ -44,9 +44,6 @@ def __init__(self, cfg, memory):
         if self.INITAL_INPUT is not None:
             self.add_to_input_queue(self.INITAL_INPUT)
 
-    def reset_vector(self, cpu_cycles, op_address, address):
-        return self.cfg.RESET_VECTOR_VALUE
-
     def add_to_input_queue(self, txt):
         log.debug("Add %s to input queue.", repr(txt))
         for char in txt:

diff --git a/dragonpy/core/configs.py b/dragonpy/core/configs.py
@@ -92,8 +92,6 @@ def __init__(self, cfg_dict):
 
         log.debug("cfg_dict: %s", repr(cfg_dict))
 
-        self.bus_addr_areas = AddressAreas(self.BUS_ADDR_AREAS)
-
         # print CPU cycle/sec while running
         self.display_cycle = cfg_dict["display_cycle"]
 

diff --git a/dragonpy/sbc09/config.py b/dragonpy/sbc09/config.py
@@ -33,9 +33,6 @@ class SBC09Cfg(BaseConfig):
     ROM_END = 0xFFFF
     ROM_SIZE = 0x4000 # 16384 Bytes
 
-    RESET_VECTOR = 0xFFFE
-    RESET_VECTOR_VALUE = 0xe400
-
     BUS_ADDR_AREAS = (
         (0xe000, 0xe001, "RS232 interface"), # emulated serial port (ACIA)
         (0xFFF2, 0xFFFE, "Interrupt vectors"),

diff --git a/dragonpy/sbc09/periphery.py b/dragonpy/sbc09/periphery.py
@@ -58,8 +58,6 @@ def __init__(self, cfg, memory):
         self.memory.add_read_byte_callback(self.read_acia_status, 0xe000) #  Control/status port of ACIA
         self.memory.add_read_byte_callback(self.read_acia_data, 0xe001) #  Data port of ACIA
 
-        self.memory.add_read_word_callback(self.reset_vector, 0xfffe)
-
         self.memory.add_write_byte_callback(self.write_acia_status, 0xe000) #  Control/status port of ACIA
         self.memory.add_write_byte_callback(self.write_acia_data, 0xe001) #  Data port of ACIA
 

diff --git a/dragonpy/tests/test_all.py b/dragonpy/tests/test_all.py
@@ -11,23 +11,21 @@
 """
 
 import unittest
-import logging
 
+from dragonpy.utils.logging_utils import setup_logging, log
 from dragonpy.tests.test_base import TextTestRunner2
 
 
-if __name__ == '__main__':
-    log = logging.getLogger("DragonPy")
-    log.setLevel(
-#         1
-#         10 # DEBUG
-#         20 # INFO
-#         30 # WARNING
-#         40 # ERROR
-        50 # CRITICAL/FATAL
+if __name__ == '__main__':   
+    setup_logging(log,
+#         level=1 # hardcore debug ;)
+#         level=10 # DEBUG
+#         level=20 # INFO
+#         level=30 # WARNING
+#         level=40 # ERROR
+#         level=50 # CRITICAL/FATAL
+        level=99
     )
-    log.addHandler(logging.StreamHandler())
-
 
     loader = unittest.TestLoader()
     tests = loader.discover('.')