The Model has been trained on the dataset created by Ajay Yadav of VDA Lab. The dataset consists of graphs of nodes which are instances of logic circuits. for more information about the dataset and usage please visit: https://github.com/ajay3568yadav/SURI
Moore Circuit Gen 1 (MCG-1) is a Graph GAN Deep Learning model trained on over 50,000 existing digital logic circuits. It can generate viable random digital logic circuits without discontinuities or improper connections.
The MCG-1 model could be beneficial for those researching and developing technology centered around FPGA and ASIC development. The ability to generate a viable random circuit allows for a model that could be further trained to generate a Register Transfer Level (RTL) design from a much higher-level circuit or description. If used properly, this technology could rapidly cut down on the production time associated with developing chips with Very Large Scale Integration that typically takes years to produce as all gates must be hand-placed to be packed into a small package.