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TOOLS: Verilator update riscv-arch-test #202: Commit e46a476 pushed by jeras
September 21, 2023 06:25 25m 30s master
master
September 21, 2023 06:25 25m 30s
TOOLS: Verilator update verible-linter #199: Commit e46a476 pushed by jeras
September 21, 2023 06:25 1m 13s master
master
September 21, 2023 06:25 1m 13s
FPGA+SIM: updated Vivado project to compile RISC-V simulation, access… riscv-arch-test #201: Commit c92b5ac pushed by jeras
August 19, 2023 15:25 35m 1s master
master
August 19, 2023 15:25 35m 1s
FPGA+SIM: updated Vivado project to compile RISC-V simulation, access… verible-linter #198: Commit c92b5ac pushed by jeras
August 19, 2023 15:25 1m 17s master
master
August 19, 2023 15:25 1m 17s
Verilator update, but still unable to handle the project riscv-arch-test #200: Commit c2106e4 pushed by jeras
August 18, 2023 20:58 28m 22s master
master
August 18, 2023 20:58 28m 22s
Verilator update, but still unable to handle the project verible-linter #197: Commit c2106e4 pushed by jeras
August 18, 2023 20:58 59s master
master
August 18, 2023 20:58 59s
SRC: added NOP into the code to allow for GPIO input data propagation… riscv-arch-test #199: Commit 2211919 pushed by jeras
August 15, 2023 09:24 15m 0s master
master
August 15, 2023 09:24 15m 0s
SRC: added NOP into the code to allow for GPIO input data propagation… verible-linter #196: Commit 2211919 pushed by jeras
August 15, 2023 09:24 1m 0s master
master
August 15, 2023 09:24 1m 0s
RTL: Degu: fixed undefined values issue caused by verilator lack of X… riscv-arch-test #198: Commit 2ecf78c pushed by jeras
August 15, 2023 09:22 20m 25s master
master
August 15, 2023 09:22 20m 25s
RTL: Degu: fixed undefined values issue caused by verilator lack of X… verible-linter #195: Commit 2ecf78c pushed by jeras
August 15, 2023 09:22 1m 2s master
master
August 15, 2023 09:22 1m 2s
HDL: replaced Degu ports with TCB interface verible-linter #194: Commit ffbab4d pushed by jeras
August 14, 2023 20:43 1m 2s master
master
August 14, 2023 20:43 1m 2s
HDL: replaced Degu ports with TCB interface riscv-arch-test #197: Commit ffbab4d pushed by jeras
August 14, 2023 20:43 17m 40s master
master
August 14, 2023 20:43 17m 40s
HDL: strted testing with new TCB version riscv-arch-test #196: Commit a56d82e pushed by jeras
August 14, 2023 16:42 18m 23s master
master
August 14, 2023 16:42 18m 23s
HDL: strted testing with new TCB version verible-linter #193: Commit a56d82e pushed by jeras
August 14, 2023 16:42 1m 32s master
master
August 14, 2023 16:42 1m 32s
FPGA: unfinished porting to newer version of TCB riscv-arch-test #195: Commit 5fa1123 pushed by jeras
August 14, 2023 02:15 17m 48s master
master
August 14, 2023 02:15 17m 48s
FPGA: unfinished porting to newer version of TCB verible-linter #192: Commit 5fa1123 pushed by jeras
August 14, 2023 02:15 1m 25s master
master
August 14, 2023 02:15 1m 25s
Xilinx: updated project to Vivado 2023.1 verible-linter #191: Commit e4466a1 pushed by jeras
August 12, 2023 15:40 1m 17s master
master
August 12, 2023 15:40 1m 17s
Xilinx: updated project to Vivado 2023.1 riscv-arch-test #194: Commit e4466a1 pushed by jeras
August 12, 2023 15:40 14m 53s master
master
August 12, 2023 15:40 14m 53s