This rule checks the alias keyword is on it's own line.
Violation
signal sig1 : std_logic; alias designator is name;
Fix
signal sig1 : std_logic;
alias designator is name;
|phase_2| |error| |whitespace|
This rule checks for a single space after the colon for the subtype_indication.
Violation
alias alias_designator : subtype_indication is name;
alias alias_designator :subtype_indication is name;
Fix
alias alias_designator : subtype_indication is name;
alias alias_designator : subtype_indication is name;
|phase_2| |error| |whitespace|
This rule checks for a single space before the is keyword if the : is present.
Violation
alias alias_designator : subtype_indication is name;
alias alias_designator is name;
Fix
alias alias_designator : subtype_indication is name;
alias alias_designator is name;
|phase_2| |error| |whitespace|
This rule checks for a single space after the is keyword.
Violation
alias alias_designator is name;
Fix
alias alias_designator is name;
This rule checks the indent of the alias keyword.
Violation
signal sig1 : integer;
alias is name;
Fix
signal sig1 : integer;
alias is name;
|phase_6| |error| |case| |case_keyword|
This rule checks the alias keyword has proper case.
|configuring_uppercase_and_lowercase_rules_link|
Violation
ALIAS alias_designator is name;
Fix
alias alias_designator is name;
|phase_6| |error| |case| |case_keyword|
This rule checks the is keyword has proper case.
|configuring_uppercase_and_lowercase_rules_link|
Violation
alias alias_designator IS name;
Fix
alias alias_designator is name;
|phase_6| |error| |case| |case_name|
This rule checks the alias designator has proper case.
|configuring_uppercase_and_lowercase_rules_link|
Violation
alias Alias_Designator is name;
Fix
alias alias_designator is name;
This rule checks for consistent capitalization of alias designators.
Violation
architecture RTL of ENTITY1 is
signal instructure : bit_vector(15 downto 0);
alias opcode : bit_vector(3 downto 0) is instructure(15 downto 12);
signal data : std_logic_vector(OPCODE'range);
begin
data <= OpCode;
PROC_NAME : process () is
begin
data <= OpCOde;
if (opCODE = "0110") then
data <= oPCode;
end if;
end process PROC_NAME;
end architecture RTL;
Fix
architecture RTL of ENTITY1 is
signal instructure : bit_vector(15 downto 0);
alias opcode : bit_vector(3 downto 0) is instructure(15 downto 12);
signal data : std_logic_vector(opcode'range);
begin
data <= opcode;
PROC_NAME : process () is
begin
data <= opcode;
if (opcode = "0110") then
data <= opcode;
end if;
end process PROC_NAME;
end architecture RTL;
|phase_7| |disabled| |error| |naming|
This rule checks for valid prefixes on alias designators.
Default prefix is a_.
|configuring_prefix_and_suffix_rules_link|
Violation
alias header is name;
alias footer is name;
Fix
alias a_header is name;
alias a_footer is name;
|phase_7| |disabled| |error| |naming|
This rule checks for valid suffixes on alias designators.
Default prefix is _a.
|configuring_prefix_and_suffix_rules_link|
Violation
alias header is name;
alias footer is name;
Fix
alias header_a is name;
alias footer_a is name;