For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
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jerralph Changed reg enums to shorten them to Xn and updated some tests. Updat…
…ed some of the raw coverage cross to ignore FENCE_I and UNKNOWN_INST
Latest commit 571fe9f Oct 17, 2018

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[ riscv-vip ]


This repository hosts RISC-V related SystemVerilog Verification IP.

See the riscv-vip users' guide for important user details. The users' guide source is in the doc/ directory and is browser viewable at

Find the release notes in the RELEASE.txt file.

Get riscv-vip

   $ git clone
   $ cd riscv-vip

Poke around the code and docs.

Run a unit test

  1. Download and install SVUnit from Follow the instructions posted there to install.
  2. Run the Hex file analyzer in the riscv-vip/src directory.
  • using the Mentor Questa Simulator.
     $ make hex_ut
  • Using the Cadence IUS Simulator
        $make hex_ut SIMR=ius

Integrate into your verification environment

See the Users' Guide for information on how to integrate into your own verification environment.