verilog-axi-formal

Formal verification for alexforencich/verilog-axi using SymbiYosys.

Simple usage:

1. Clone this repo and update the submodule

   git clone https://github.com/jimmysitu/verilog-axi-formal.git
   git submodule update --init --recursive

2. Run formal verification with SymbiYosys

   cd formal
   make axil_ram