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ALU.fir
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ALU.fir
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;buildInfoPackage: chisel3, version: 3.4.3, scalaVersion: 2.12.12, sbtVersion: 1.3.10
circuit ALU :
module ALU :
input clock : Clock
input reset : UInt<1>
output io : {flip opcode : UInt<7>, flip in_a : UInt<64>, flip in_b : UInt<64>, out_a : UInt<64>, out_b : UInt<64>, flip validin_a : UInt<1>, flip validin_b : UInt<1>, validout_a : UInt<1>, validout_b : UInt<1>}
reg snapshot_a : UInt<64>, clock with : (reset => (reset, UInt<64>("h00"))) @[ALU.scala 23:27]
reg snapshot_valid_a : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[ALU.scala 25:33]
reg temp_result_a : UInt<64>, clock with : (reset => (reset, UInt<64>("h00"))) @[ALU.scala 28:30]
reg temp_result_b : UInt<64>, clock with : (reset => (reset, UInt<64>("h00"))) @[ALU.scala 29:30]
reg temp_valid_a : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[ALU.scala 32:29]
reg temp_valid_b : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[ALU.scala 33:29]
node _opcode_T = bits(io.opcode, 0, 0) @[ALU.scala 36:34]
node _opcode_T_1 = bits(io.opcode, 1, 1) @[ALU.scala 36:34]
node _opcode_T_2 = bits(io.opcode, 2, 2) @[ALU.scala 36:34]
node _opcode_T_3 = bits(io.opcode, 3, 3) @[ALU.scala 36:34]
node _opcode_T_4 = bits(io.opcode, 4, 4) @[ALU.scala 36:34]
node _opcode_T_5 = bits(io.opcode, 5, 5) @[ALU.scala 36:34]
node _opcode_T_6 = bits(io.opcode, 6, 6) @[ALU.scala 36:34]
wire opcode : UInt<1>[7] @[ALU.scala 36:23]
opcode[0] <= _opcode_T @[ALU.scala 36:23]
opcode[1] <= _opcode_T_1 @[ALU.scala 36:23]
opcode[2] <= _opcode_T_2 @[ALU.scala 36:23]
opcode[3] <= _opcode_T_3 @[ALU.scala 36:23]
opcode[4] <= _opcode_T_4 @[ALU.scala 36:23]
opcode[5] <= _opcode_T_5 @[ALU.scala 36:23]
opcode[6] <= _opcode_T_6 @[ALU.scala 36:23]
wire gate_a : UInt<64>
gate_a <= UInt<64>("h00")
wire gate_b : UInt<64>
gate_b <= UInt<64>("h00")
wire gate_valid_a : UInt<1>
gate_valid_a <= UInt<1>("h00")
wire gate_valid_b : UInt<1>
gate_valid_b <= UInt<1>("h00")
node _T = eq(opcode[6], UInt<1>("h00")) @[ALU.scala 43:18]
when _T : @[ALU.scala 43:26]
node _T_1 = eq(opcode[5], UInt<1>("h01")) @[ALU.scala 44:20]
node _T_2 = eq(opcode[4], UInt<1>("h01")) @[ALU.scala 44:41]
node _T_3 = and(_T_1, _T_2) @[ALU.scala 44:28]
when _T_3 : @[ALU.scala 44:49]
node _temp_result_a_T = and(gate_a, gate_b) @[ALU.scala 45:33]
node _temp_result_a_T_1 = not(_temp_result_a_T) @[ALU.scala 45:24]
temp_result_a <= _temp_result_a_T_1 @[ALU.scala 45:21]
skip @[ALU.scala 44:49]
else : @[ALU.scala 46:16]
node _temp_result_a_T_2 = and(gate_a, gate_b) @[ALU.scala 47:31]
temp_result_a <= _temp_result_a_T_2 @[ALU.scala 47:21]
skip @[ALU.scala 46:16]
skip @[ALU.scala 43:26]
else : @[ALU.scala 49:33]
node _T_4 = eq(opcode[6], UInt<1>("h01")) @[ALU.scala 49:25]
when _T_4 : @[ALU.scala 49:33]
node _T_5 = eq(opcode[5], UInt<1>("h01")) @[ALU.scala 50:20]
node _T_6 = eq(opcode[4], UInt<1>("h01")) @[ALU.scala 50:41]
node _T_7 = and(_T_5, _T_6) @[ALU.scala 50:28]
when _T_7 : @[ALU.scala 50:49]
node _temp_result_a_T_3 = or(gate_a, gate_b) @[ALU.scala 51:33]
node _temp_result_a_T_4 = not(_temp_result_a_T_3) @[ALU.scala 51:24]
temp_result_a <= _temp_result_a_T_4 @[ALU.scala 51:21]
skip @[ALU.scala 50:49]
else : @[ALU.scala 52:16]
node _temp_result_a_T_5 = or(gate_a, gate_b) @[ALU.scala 53:31]
temp_result_a <= _temp_result_a_T_5 @[ALU.scala 53:21]
skip @[ALU.scala 52:16]
skip @[ALU.scala 49:33]
node _T_8 = eq(opcode[5], UInt<1>("h00")) @[ALU.scala 57:18]
node _T_9 = eq(opcode[4], UInt<1>("h00")) @[ALU.scala 57:39]
node _T_10 = and(_T_8, _T_9) @[ALU.scala 57:26]
when _T_10 : @[ALU.scala 57:47]
node _T_11 = eq(opcode[3], UInt<1>("h00")) @[ALU.scala 58:20]
when _T_11 : @[ALU.scala 58:28]
gate_a <= io.in_a @[ALU.scala 59:14]
gate_b <= io.in_b @[ALU.scala 60:14]
gate_valid_a <= io.validin_a @[ALU.scala 61:20]
gate_valid_b <= io.validin_b @[ALU.scala 62:20]
skip @[ALU.scala 58:28]
else : @[ALU.scala 63:35]
node _T_12 = eq(opcode[3], UInt<1>("h01")) @[ALU.scala 63:27]
when _T_12 : @[ALU.scala 63:35]
gate_a <= snapshot_a @[ALU.scala 64:14]
gate_b <= io.in_b @[ALU.scala 65:14]
gate_valid_a <= snapshot_valid_a @[ALU.scala 66:20]
gate_valid_b <= io.validin_b @[ALU.scala 67:20]
skip @[ALU.scala 63:35]
skip @[ALU.scala 57:47]
else : @[ALU.scala 69:54]
node _T_13 = eq(opcode[5], UInt<1>("h00")) @[ALU.scala 69:25]
node _T_14 = eq(opcode[4], UInt<1>("h01")) @[ALU.scala 69:46]
node _T_15 = and(_T_13, _T_14) @[ALU.scala 69:33]
when _T_15 : @[ALU.scala 69:54]
node _T_16 = eq(opcode[3], UInt<1>("h00")) @[ALU.scala 70:20]
when _T_16 : @[ALU.scala 70:28]
node _gate_a_T = not(io.in_a) @[ALU.scala 71:17]
gate_a <= _gate_a_T @[ALU.scala 71:14]
gate_b <= io.in_b @[ALU.scala 72:14]
gate_valid_a <= io.validin_a @[ALU.scala 73:20]
gate_valid_b <= io.validin_b @[ALU.scala 74:20]
skip @[ALU.scala 70:28]
else : @[ALU.scala 75:35]
node _T_17 = eq(opcode[3], UInt<1>("h01")) @[ALU.scala 75:27]
when _T_17 : @[ALU.scala 75:35]
node _gate_a_T_1 = not(snapshot_a) @[ALU.scala 76:17]
gate_a <= _gate_a_T_1 @[ALU.scala 76:14]
gate_b <= io.in_b @[ALU.scala 77:14]
gate_valid_a <= snapshot_valid_a @[ALU.scala 78:20]
gate_valid_b <= io.validin_b @[ALU.scala 79:20]
skip @[ALU.scala 75:35]
skip @[ALU.scala 69:54]
else : @[ALU.scala 81:54]
node _T_18 = eq(opcode[5], UInt<1>("h01")) @[ALU.scala 81:25]
node _T_19 = eq(opcode[4], UInt<1>("h00")) @[ALU.scala 81:46]
node _T_20 = and(_T_18, _T_19) @[ALU.scala 81:33]
when _T_20 : @[ALU.scala 81:54]
node _T_21 = eq(opcode[3], UInt<1>("h00")) @[ALU.scala 82:20]
when _T_21 : @[ALU.scala 82:28]
gate_a <= io.in_a @[ALU.scala 83:14]
node _gate_b_T = not(io.in_b) @[ALU.scala 84:17]
gate_b <= _gate_b_T @[ALU.scala 84:14]
gate_valid_a <= io.validin_a @[ALU.scala 85:20]
gate_valid_b <= io.validin_b @[ALU.scala 86:20]
skip @[ALU.scala 82:28]
else : @[ALU.scala 87:35]
node _T_22 = eq(opcode[3], UInt<1>("h01")) @[ALU.scala 87:27]
when _T_22 : @[ALU.scala 87:35]
gate_a <= snapshot_a @[ALU.scala 88:14]
node _gate_b_T_1 = not(io.in_b) @[ALU.scala 89:17]
gate_b <= _gate_b_T_1 @[ALU.scala 89:14]
gate_valid_a <= snapshot_valid_a @[ALU.scala 90:20]
gate_valid_b <= io.validin_b @[ALU.scala 91:20]
skip @[ALU.scala 87:35]
skip @[ALU.scala 81:54]
else : @[ALU.scala 93:54]
node _T_23 = eq(opcode[5], UInt<1>("h01")) @[ALU.scala 93:25]
node _T_24 = eq(opcode[4], UInt<1>("h01")) @[ALU.scala 93:46]
node _T_25 = and(_T_23, _T_24) @[ALU.scala 93:33]
when _T_25 : @[ALU.scala 93:54]
node _T_26 = eq(opcode[3], UInt<1>("h00")) @[ALU.scala 94:20]
when _T_26 : @[ALU.scala 94:28]
gate_a <= io.in_a @[ALU.scala 95:14]
gate_b <= io.in_b @[ALU.scala 96:14]
gate_valid_a <= io.validin_a @[ALU.scala 97:20]
gate_valid_b <= io.validin_b @[ALU.scala 98:20]
skip @[ALU.scala 94:28]
else : @[ALU.scala 99:35]
node _T_27 = eq(opcode[3], UInt<1>("h01")) @[ALU.scala 99:27]
when _T_27 : @[ALU.scala 99:35]
gate_a <= snapshot_a @[ALU.scala 100:14]
gate_b <= io.in_b @[ALU.scala 101:14]
gate_valid_a <= snapshot_valid_a @[ALU.scala 102:20]
gate_valid_b <= io.validin_b @[ALU.scala 103:20]
skip @[ALU.scala 99:35]
skip @[ALU.scala 93:54]
node _T_28 = eq(opcode[2], UInt<1>("h00")) @[ALU.scala 107:18]
when _T_28 : @[ALU.scala 107:26]
snapshot_a <= snapshot_a @[ALU.scala 108:16]
snapshot_valid_a <= snapshot_valid_a @[ALU.scala 109:22]
skip @[ALU.scala 107:26]
else : @[ALU.scala 110:33]
node _T_29 = eq(opcode[2], UInt<1>("h01")) @[ALU.scala 110:25]
when _T_29 : @[ALU.scala 110:33]
snapshot_a <= io.in_a @[ALU.scala 111:16]
snapshot_valid_a <= io.validin_a @[ALU.scala 112:22]
skip @[ALU.scala 110:33]
node _T_30 = eq(opcode[1], UInt<1>("h00")) @[ALU.scala 115:18]
node _T_31 = eq(opcode[0], UInt<1>("h00")) @[ALU.scala 115:39]
node _T_32 = and(_T_30, _T_31) @[ALU.scala 115:26]
when _T_32 : @[ALU.scala 115:47]
temp_valid_a <= UInt<1>("h00") @[ALU.scala 116:18]
temp_valid_b <= UInt<1>("h00") @[ALU.scala 117:18]
temp_result_b <= io.in_b @[ALU.scala 118:19]
skip @[ALU.scala 115:47]
else : @[ALU.scala 119:54]
node _T_33 = eq(opcode[1], UInt<1>("h00")) @[ALU.scala 119:25]
node _T_34 = eq(opcode[0], UInt<1>("h01")) @[ALU.scala 119:46]
node _T_35 = and(_T_33, _T_34) @[ALU.scala 119:33]
when _T_35 : @[ALU.scala 119:54]
node _temp_valid_a_T = and(gate_valid_a, gate_valid_b) @[ALU.scala 120:34]
temp_valid_a <= _temp_valid_a_T @[ALU.scala 120:18]
temp_valid_b <= UInt<1>("h00") @[ALU.scala 121:18]
temp_result_b <= io.in_b @[ALU.scala 122:19]
skip @[ALU.scala 119:54]
else : @[ALU.scala 123:54]
node _T_36 = eq(opcode[1], UInt<1>("h01")) @[ALU.scala 123:25]
node _T_37 = eq(opcode[0], UInt<1>("h00")) @[ALU.scala 123:46]
node _T_38 = and(_T_36, _T_37) @[ALU.scala 123:33]
when _T_38 : @[ALU.scala 123:54]
node _temp_valid_a_T_1 = and(gate_valid_a, gate_valid_b) @[ALU.scala 124:34]
temp_valid_a <= _temp_valid_a_T_1 @[ALU.scala 124:18]
temp_valid_b <= io.validin_a @[ALU.scala 125:18]
temp_result_b <= io.in_a @[ALU.scala 126:19]
skip @[ALU.scala 123:54]
else : @[ALU.scala 127:54]
node _T_39 = eq(opcode[1], UInt<1>("h01")) @[ALU.scala 127:25]
node _T_40 = eq(opcode[0], UInt<1>("h01")) @[ALU.scala 127:46]
node _T_41 = and(_T_39, _T_40) @[ALU.scala 127:33]
when _T_41 : @[ALU.scala 127:54]
node _temp_valid_a_T_2 = and(gate_valid_a, gate_valid_b) @[ALU.scala 128:34]
temp_valid_a <= _temp_valid_a_T_2 @[ALU.scala 128:18]
temp_valid_b <= io.validin_b @[ALU.scala 129:18]
temp_result_b <= io.in_b @[ALU.scala 130:19]
skip @[ALU.scala 127:54]
io.out_a <= temp_result_a @[ALU.scala 1314:12]
io.out_b <= temp_result_b @[ALU.scala 1315:12]
io.validout_a <= temp_valid_a @[ALU.scala 1316:17]
io.validout_b <= temp_valid_b @[ALU.scala 1317:17]