removed counter config from demos

jjjt-git · Jan 31, 2024 · 20f638e · 20f638e
1 parent 248ad24
commit 20f638e
Show file tree

Hide file tree

Showing 7 changed files with 8 additions and 41 deletions.
diff --git a/src/main/scala/vexriscv/demo/Briey.scala b/src/main/scala/vexriscv/demo/Briey.scala
@@ -146,12 +146,8 @@ object BrieyConfig{
             mscratchGen    = false,
             mcauseAccess   = CsrAccess.READ_ONLY,
             mbadaddrAccess = CsrAccess.READ_ONLY,
-            mcycleAccess   = CsrAccess.NONE,
-            minstretAccess = CsrAccess.NONE,
             ecallGen       = false,
-            wfiGenAsWait         = false,
-            ucycleAccess   = CsrAccess.NONE,
-            uinstretAccess = CsrAccess.NONE
+            wfiGenAsWait         = false
           )
         ),
         new YamlPlugin("cpu0.yaml")

diff --git a/src/main/scala/vexriscv/demo/VexRiscvAhbLite3.scala b/src/main/scala/vexriscv/demo/VexRiscvAhbLite3.scala
@@ -122,12 +122,8 @@ object VexRiscvAhbLite3{
               mscratchGen    = false,
               mcauseAccess   = CsrAccess.READ_ONLY,
               mbadaddrAccess = CsrAccess.READ_ONLY,
-              mcycleAccess   = CsrAccess.NONE,
-              minstretAccess = CsrAccess.NONE,
               ecallGen       = false,
-              wfiGenAsWait         = false,
-              ucycleAccess   = CsrAccess.NONE,
-              uinstretAccess = CsrAccess.NONE
+              wfiGenAsWait         = false
             )
           ),
           new YamlPlugin("cpu0.yaml")

diff --git a/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala b/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala
@@ -120,12 +120,8 @@ object VexRiscvAvalonForSim{
               mscratchGen    = false,
               mcauseAccess   = CsrAccess.READ_ONLY,
               mbadaddrAccess = CsrAccess.READ_ONLY,
-              mcycleAccess   = CsrAccess.NONE,
-              minstretAccess = CsrAccess.NONE,
               ecallGen       = false,
-              wfiGenAsWait         = false,
-              ucycleAccess   = CsrAccess.NONE,
-              uinstretAccess = CsrAccess.NONE
+              wfiGenAsWait         = false
             )
           ),
           new YamlPlugin("cpu0.yaml")

diff --git a/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala b/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala
@@ -117,12 +117,8 @@ object VexRiscvAvalonWithIntegratedJtag{
               mscratchGen    = false,
               mcauseAccess   = CsrAccess.READ_ONLY,
               mbadaddrAccess = CsrAccess.READ_ONLY,
-              mcycleAccess   = CsrAccess.NONE,
-              minstretAccess = CsrAccess.NONE,
               ecallGen       = false,
-              wfiGenAsWait         = false,
-              ucycleAccess   = CsrAccess.NONE,
-              uinstretAccess = CsrAccess.NONE
+              wfiGenAsWait         = false
             )
           ),
           new YamlPlugin("cpu0.yaml")

diff --git a/src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala b/src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala
@@ -118,12 +118,8 @@ object VexRiscvAxi4WithIntegratedJtag{
               mscratchGen    = false,
               mcauseAccess   = CsrAccess.READ_ONLY,
               mbadaddrAccess = CsrAccess.READ_ONLY,
-              mcycleAccess   = CsrAccess.NONE,
-              minstretAccess = CsrAccess.NONE,
               ecallGen       = false,
-              wfiGenAsWait         = false,
-              ucycleAccess   = CsrAccess.NONE,
-              uinstretAccess = CsrAccess.NONE
+              wfiGenAsWait         = false
             )
           ),
           new YamlPlugin("cpu0.yaml")

diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
@@ -208,11 +208,7 @@ object VexRiscvSmpClusterGen {
       if(csrFull){
        c = c.copy(
          mcauseAccess   = CsrAccess.READ_WRITE,
-         mbadaddrAccess = CsrAccess.READ_WRITE,
-         ucycleAccess   = CsrAccess.READ_ONLY,
-         uinstretAccess = CsrAccess.READ_ONLY,
-         mcycleAccess   = CsrAccess.READ_WRITE,
-         minstretAccess = CsrAccess.READ_WRITE
+         mbadaddrAccess = CsrAccess.READ_WRITE
        )
       }
       c
@@ -232,13 +228,10 @@ object VexRiscvSmpClusterGen {
         mscratchGen    = forceMscratch,
         mcauseAccess   = CsrAccess.READ_ONLY,
         mbadaddrAccess = CsrAccess.READ_ONLY,
-        mcycleAccess   = CsrAccess.NONE,
-        minstretAccess = CsrAccess.NONE,
         ecallGen       = true,
         ebreakGen      = true,
         wfiGenAsWait   = false,
         wfiGenAsNop    = true,
-        ucycleAccess   = CsrAccess.NONE,
         withPrivilegedDebug = privilegedDebug
       )
     }

diff --git a/src/test/scala/vexriscv/experimental/GenMicro.scala b/src/test/scala/vexriscv/experimental/GenMicro.scala
@@ -93,13 +93,10 @@ object GenMicro extends App{
             mscratchGen    = false,
             mcauseAccess   = CsrAccess.READ_ONLY,
             mbadaddrAccess = CsrAccess.NONE,
-            mcycleAccess   = CsrAccess.NONE,
-            minstretAccess = CsrAccess.NONE,
             ecallGen       = false,
             ebreakGen      = false,
             wfiGenAsWait         = false,
             wfiGenAsNop    = false,
-            ucycleAccess   = CsrAccess.NONE,
             noCsrAlu       = true
           ) else CsrPluginConfig(
             catchIllegalAccess = false,
@@ -115,13 +112,10 @@ object GenMicro extends App{
             mscratchGen    = true,
             mcauseAccess   = CsrAccess.READ_ONLY,
             mbadaddrAccess = CsrAccess.READ_ONLY,
-            mcycleAccess   = CsrAccess.NONE,
-            minstretAccess = CsrAccess.NONE,
             ecallGen       = true,
             ebreakGen      = true,
             wfiGenAsWait   = false,
-            wfiGenAsNop    = true,
-            ucycleAccess   = CsrAccess.NONE
+            wfiGenAsNop    = true
           )
         )))
       )
@@ -159,4 +153,4 @@ object GenMicroSynthesis {
 
     Bench(rtls, targets, "/eda/tmp/")
   }
-}
+}