Cordic_Test_tb.vcd

$date
	Fri Jan 03 18:15:22 2020
$end
$version
	Icarus Verilog
$end
$timescale
	1ps
$end
$scope module Cordic_Test_tb $end
$var wire 32 ! Sin [31:0] $end
$var wire 32 " Error [31:0] $end
$var wire 32 # Cos [31:0] $end
$var reg 1 $ CLK_50M $end
$var reg 32 % Phase [31:0] $end
$var reg 32 & Phase_n [31:0] $end
$var reg 1 ' RST_N $end
$var reg 16 ( cnt [15:0] $end
$var reg 16 ) cnt_n [15:0] $end
$scope module uut $end
$var wire 1 $ CLK_50M $end
$var wire 32 * Phase [31:0] $end
$var wire 1 ' RST_N $end
$var reg 32 + Cos [31:0] $end
$var reg 32 , Error [31:0] $end
$var reg 32 - Sin [31:0] $end
$var reg 32 . x0 [31:0] $end
$var reg 32 / x1 [31:0] $end
$var reg 32 0 x10 [31:0] $end
$var reg 32 1 x11 [31:0] $end
$var reg 32 2 x12 [31:0] $end
$var reg 32 3 x13 [31:0] $end
$var reg 32 4 x14 [31:0] $end
$var reg 32 5 x15 [31:0] $end
$var reg 32 6 x16 [31:0] $end
$var reg 32 7 x2 [31:0] $end
$var reg 32 8 x3 [31:0] $end
$var reg 32 9 x4 [31:0] $end
$var reg 32 : x5 [31:0] $end
$var reg 32 ; x6 [31:0] $end
$var reg 32 < x7 [31:0] $end
$var reg 32 = x8 [31:0] $end
$var reg 32 > x9 [31:0] $end
$var reg 32 ? y0 [31:0] $end
$var reg 32 @ y1 [31:0] $end
$var reg 32 A y10 [31:0] $end
$var reg 32 B y11 [31:0] $end
$var reg 32 C y12 [31:0] $end
$var reg 32 D y13 [31:0] $end
$var reg 32 E y14 [31:0] $end
$var reg 32 F y15 [31:0] $end
$var reg 32 G y16 [31:0] $end
$var reg 32 H y2 [31:0] $end
$var reg 32 I y3 [31:0] $end
$var reg 32 J y4 [31:0] $end
$var reg 32 K y5 [31:0] $end
$var reg 32 L y6 [31:0] $end
$var reg 32 M y7 [31:0] $end
$var reg 32 N y8 [31:0] $end
$var reg 32 O y9 [31:0] $end
$var reg 32 P z0 [31:0] $end
$var reg 32 Q z1 [31:0] $end
$var reg 32 R z10 [31:0] $end
$var reg 32 S z11 [31:0] $end
$var reg 32 T z12 [31:0] $end
$var reg 32 U z13 [31:0] $end
$var reg 32 V z14 [31:0] $end
$var reg 32 W z15 [31:0] $end
$var reg 32 X z16 [31:0] $end
$var reg 32 Y z2 [31:0] $end
$var reg 32 Z z3 [31:0] $end
$var reg 32 [ z4 [31:0] $end
$var reg 32 \ z5 [31:0] $end
$var reg 32 ] z6 [31:0] $end
$var reg 32 ^ z7 [31:0] $end
$var reg 32 _ z8 [31:0] $end
$var reg 32 ` z9 [31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
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$end
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