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jlong299/README.md
  • 👋 Hi, I’m @jlong299
  • 👀 I’m interested in RISC-V CPU & VPU design

Popular repositories Loading

  1. riscv-vector-interface riscv-vector-interface Public

    FVI (Flexible RISC-V Vector Interface) is a high-performance interface designed to connect a RISC-V vector core with a scalar core.

    3 1

  2. jlong299.github.io jlong299.github.io Public

    HTML

  3. jlong299 jlong299 Public

    Config files for my GitHub profile.

  4. riscv-vector riscv-vector Public

    Forked from IntelLabs/riscv-vector

    Vector Acceleration IP core for RISC-V*

    Scala

  5. chisel-template-simple chisel-template-simple Public

    A simple template of Chisel project

    Scala