Parameterize memory block sizes and modularize specific memory code

[jardhu]

The memory is currently hardcoded to handle 32-bit block sizes. This is sufficient for our current purposes, but for involved implementations like caches which usually use 64-bit blocks we must be able to support arbitrary block sizes.

This will be best done with a blocksize parameter included in the CPU's configuration. This will be passed along with the latency into the backing memory and instruction/data memory ports' constructors, which initialize the inner wiring with the appropriate bit widths. I attempted to do this in one single side commit but there were clearly some aspects of the memory that required a more directed, thoughtful approach to parameterization.

We should also split the memory mask mode and sign-extension code into a function
and generalize the logic for any block size. At this moment the synchronous and async memory both use the same copy-pasted masking and sign-extension logic, and both instances are hardcoded to 32 bit block widths. Splitting this into its own function would make debugging and maintenance much easier for us.