65c02_core

This is a work in progress, hopefully a 65c02 core implementing the 65c02 ISA. This is an early alpha and, while all the connections between the various registers and signals are there, the control logic, and the ISA, has not yet been implemented. My first shot at the ALU is done, and it is ready to test.

Right now, I'm designing for the Xilinx Artix-7 series, with a CMOD A7 stand-in for the moment (because it has SRAM onboard).

If you want to simulate timing and function, make sure to cycle "reset" once before starting.

Name		Name	Last commit message	Last commit date
Latest commit History 20 Commits
c_addsub_0		c_addsub_0
clk_wiz_0		clk_wiz_0
dist_mem_gen_0		dist_mem_gen_0
processor_block		processor_block
ALU.sv		ALU.sv
Cmod-A7-Master.xdc		Cmod-A7-Master.xdc
Input_Data_Latch.sv		Input_Data_Latch.sv
JM65C02S.sv		JM65C02S.sv
JM65C02S.xpr		JM65C02S.xpr
LICENSE		LICENSE
PCH.sv		PCH.sv
PCL.sv		PCL.sv
README.md		README.md
accumulator_A.sv		accumulator_A.sv
address_bus.sv		address_bus.sv
bcd_to_bin.v		bcd_to_bin.v
bin_to_bcd.v		bin_to_bcd.v
clocking_unit.sv		clocking_unit.sv
data_bus.sv		data_bus.sv
data_bus_buffer.sv		data_bus_buffer.sv
index_register_X.sv		index_register_X.sv
index_register_Y.sv		index_register_Y.sv
instruction_decode.sv		instruction_decode.sv
instruction_register.sv		instruction_register.sv
interrupt_logic.sv		interrupt_logic.sv
microcode_test.sv		microcode_test.sv
processor_stat_reg.sv		processor_stat_reg.sv
processor_wrapper.v		processor_wrapper.v
processor_wrapper_behav.wcfg		processor_wrapper_behav.wcfg
stack_point_register.sv		stack_point_register.sv
timing_control.sv		timing_control.sv

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jmstein7/65c02_core

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