Verilog Examples

File ending

.v  // Verilog 2001 standard
.sv // SystemVerilog 2006 standard, forces some tools to use newer standards

Comments

// Single line comment
/*
    Multi-line commment
*/

Module

module <name> #(
    <params>
)(
    <ports>
);
    <params>
    <regs>
    <wires>
    <ints>
    <proc>
    <ass>
endmodule

Ports

input <name>,               // Input
input [x:y] <name>, <name>, // Multiple array "x downto y" inputs
inout reg <name>,           // Simultaneus in- and output register
output <name>               // Output

Registers / Wires

reg <type> <name>, <name>; // Registers (Save Data at end of clock cycle)
wire <type> [x:y] <name>;  // Wire "from x downto y" (Transmits data almost instantly)
reg a = 0;                 // With initial value this time (mostly for sim)

Parameters aka Generics & Constants

parameter <type> <name>;            // Generic (in port definition)
parameter <type> <name> = <value>;  // Constant
localparam <type> <name> = <value>; // Constant inside module (can be computed from generics)

Instantiation

Syntax

// Ports & params separated by ","
<module> #(
    <params>
) <instance> (
    <ports>
);

Port and Parameter assignments

.<port>(<connection/value>)
.<parameter(<connection/value>)

Processes

Always @

always @ (<condition>) <actions>

Intitial (Sim only!)

initial <stmt>
initial begin
    <stmts>
end

Clock

posedge clk // Rising edge of clock
negedge clk // Falling edge o clock
posedge rst // Rising edge of reset

Conditions

If

if (<condition1>) begin
    <stmts>
end else if (<condition>) begin
    <stmts>
end else begin
    <stmts>
end

Switch / Case

case (<expr>)
    <value> : begin
        <stmts>
    end
    <value> : begin
        <stmts>
    end
    default : begin
        <stmts>
    end
endcase

case (<expr>)
    2'bxz : <expr>;
    2'bzx : <expr>;
    2'bxx : <expr>;
    default : <expr>;
endcase

Assignments

Assign all indices

assign x = '1;        // Assign whole vector to logical one (zero works too)
assign x = 25'd69;
assign x = (a ? b : c); // Assign a if b (condition) else assign c to x

Values

Interpreted Types

-7 46 123      // Integer
1.3 0.2 3e-5   // Real
"Hello kitty!" // String

Logical Values

0 // Logical zero
1 // Logical one
x // Unknown/undefined
z // What the actual f*ck

Logical radix

'd46 'D23 // Decimal
'hFA 'HAE // Hexadecimal
'o17 'O77 // Octal
'b10 'b01 // Binary

Length

<bitlen>'<format><value>
32'd46                   // 32 bit filled with (one!) decimal 46
8'b10101010              // "10101010" in binary as 8 bit-value
18'o777777               // 18 bits of ones from octal code

Types

Builtin Types

// Can be interpreted by totally not stupid compiler that will totally not produce untraceable errors
logic   // Standard logic
real
string
time    // For simulations
event   // Complex (probably represents change of value of sens list connections / sens list itself)
int
int []  // Dynamic size array for integer
integer

Custom Types

// Elements separated by ","
typedef logic [x:y] <name>;      // Arrays
typedef enum state {<e>} <name>; // For united states machines
typedef enum {<e>} <name>;       // Not a state enum bruh
typedef enum [x:y] {<e>} <name>; // Enum with specified range

Operators

Logical Operators

!  // Logical negation
&& // Logical and
|| // Logical or

Arithmetic Operators

+   // Addition
++  // Increment by 1
-   // Subtraction
--  // Decrement by 1
*   // Multiplication
/   // Division
%   // Modulus
**  // Exponentiation
<<< // Arithmetic left shift (<expr> <<< <expr>), fills by type
>>> // Arithmetic right shift (<expr> >>> <expr>), fills by type

Bitwise Operators

~  // Bitwise negation
&  // Bitwise and
~& // Bitwise nand
|  // Bitwise or
~| // Bitwise nor
^  // Bitwise xor
~^ // Bitwise xnor
<< // Bitwise left shift (<expr> << <expr>), fills with 0
>> // Bitwise right shift (<expr> >> <expr>), fills with 0

Assignment Operators

=  // Blocking asmt blocks access from other processes
<= // Nonblocking asmt allows simultaneous access

Comparative Operators

>   // Greater than
>=  // Greater than or equal to
<   // Smaller than
<=  // Smaller than or equal to
==  // Logical equality
!=  // Logical equality
=== // Case equality (includes x, z, recommend sim only)
!== // Case inequality (includes x, z, recommend sim only)

Packages

package <name>
    <params>
    <funcs?>
    <types>
endpackage

Functions

Builtin

Math

$sin   // Sinus
$cos   // Cosinus
$tan   // Tangens
$ln    // Natural logarithm
$clog2 // Logarithm base 2
$pow   // Power function

System (Sim only!)

$display // Output to console 
$finish  // Shut down simulation
$stop    // Suspend sim in interactive mode, in 0 for minimal info, 2 for max
$time    // Output sim time
#<expr>  // Wait (delay) operator delays by <expr> time

Declaration

function <return> <name> (<input>);
    begin
        <stmts>
    end
endfunction