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Jonas Blixt committed Dec 6, 2023
1 parent ad25da6 commit bc1c069
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Showing 5 changed files with 308 additions and 304 deletions.
128 changes: 73 additions & 55 deletions include/drivers/memc/imx_flexspi.h
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Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
/**
* Punch BOOT
*
* Copyright (C) 2023 Jonas Blixt <jonpe960@gmail.com>
* Copyright (C) 2023 Marten Svanfeldt <marten.svanfeldt@actia.se>
*
* SPDX-License-Identifier: BSD-3-Clause
Expand All @@ -12,13 +13,27 @@

#include <stdint.h>

#define FLEXSPI_1PAD 0
#define FLEXSPI_2PAD 1
#define FLEXSPI_4PAD 2
#define FLEXSPI_8PAD 3
#define FLEXSPI_CR1_CS_INTERVAL(x) ((x & 0xffff) << 16)
#define FLEXSPI_CR1_CS_INTERVAL_UNIT (1 << 15)
#define FLEXSPI_CR1_CAS(x) ((x & 0x0f) << 11)
#define FLEXSPI_CR1_WA (1 << 10)
#define FLEXSPI_CR1_TCSH(x) ((x & 0x1F) << 5)
#define FLEXSPI_CR1_TCSS(x) (x & 0x1F)

#define FLEXSPI_LUT_OPERAND0_MASK (0xffu)
#define FLEXSPI_LUT_OPERAND0_SHIFT (0U)
#define FLEXSPI_CR2_ARDSEQNUM(x) ((x & 0x07) << 5)
#define FLEXSPI_CR2_ARDSEQID(x) (x & 0x0f)

#define FLEXSPI_CR4_WMOPT1 BIT(0)

#define FLEXSPI_DLLCR_OVRDEN BIT(8)

#define FLEXSPI_1PAD 0
#define FLEXSPI_2PAD 1
#define FLEXSPI_4PAD 2
#define FLEXSPI_8PAD 3

#define FLEXSPI_LUT_OPERAND0_MASK (0xffu)
#define FLEXSPI_LUT_OPERAND0_SHIFT (0U)
#define FLEXSPI_LUT_OPERAND0(x) \
(((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)
#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300u)
Expand Down Expand Up @@ -46,7 +61,6 @@
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | \
FLEXSPI_LUT_OPERAND1(op1) | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))


enum flexspi_port {
FLEXSPI_PORT_A1 = 0x0U, /*!< Access flash on A1 port. */
FLEXSPI_PORT_A2, /*!< Access flash on A2 port. */
Expand All @@ -56,60 +70,52 @@ enum flexspi_port {
};

enum flexspi_command_type {
kFLEXSPI_Command, /*!< FlexSPI operation: Only command, both TX and Rx buffer are ignored. */
kFLEXSPI_Config, /*!< FlexSPI operation: Configure device mode, the TX fifo size is fixed in
FLEXSPI_COMMAND, /*!< FlexSPI operation: Only command, both TX and Rx buffer are ignored. */
FLEXSPI_CONFIG, /*!< FlexSPI operation: Configure device mode, the TX fifo size is fixed in
LUT. */
kFLEXSPI_Read, /* /!< FlexSPI operation: Read, only Rx Buffer is effective. */
kFLEXSPI_Write, /* /!< FlexSPI operation: Read, only Tx Buffer is effective. */
FLEXSPI_READ, /* /!< FlexSPI operation: Read, only Rx Buffer is effective. */
FLEXSPI_WRITE, /* /!< FlexSPI operation: Read, only Tx Buffer is effective. */
};

enum flexspi_command {
kFLEXSPI_Command_STOP = 0x00U, /*!< Stop execution, deassert CS. */
kFLEXSPI_Command_SDR = 0x01U, /*!< Transmit Command code to Flash, using SDR mode. */
kFLEXSPI_Command_RADDR_SDR = 0x02U, /*!< Transmit Row Address to Flash, using SDR mode. */
kFLEXSPI_Command_CADDR_SDR = 0x03U, /*!< Transmit Column Address to Flash, using SDR mode. */
kFLEXSPI_Command_MODE1_SDR = 0x04U, /*!< Transmit 1-bit Mode bits to Flash, using SDR mode. */
kFLEXSPI_Command_MODE2_SDR = 0x05U, /*!< Transmit 2-bit Mode bits to Flash, using SDR mode. */
kFLEXSPI_Command_MODE4_SDR = 0x06U, /*!< Transmit 4-bit Mode bits to Flash, using SDR mode. */
kFLEXSPI_Command_MODE8_SDR = 0x07U, /*!< Transmit 8-bit Mode bits to Flash, using SDR mode. */
kFLEXSPI_Command_WRITE_SDR = 0x08U, /*!< Transmit Programming Data to Flash, using SDR mode. */
kFLEXSPI_Command_READ_SDR = 0x09U, /*!< Receive Read Data from Flash, using SDR mode. */
kFLEXSPI_Command_LEARN_SDR = 0x0AU, /*!< Receive Read Data or Preamble bit from Flash, SDR mode.
*/
kFLEXSPI_Command_DATSZ_SDR = 0x0BU, /*!< Transmit Read/Program Data size (byte) to Flash, SDR
FLEXSPI_COMMAND_STOP = 0x00U, /*!< Stop execution, deassert CS. */
FLEXSPI_COMMAND_SDR = 0x01U, /*!< Transmit Command code to Flash, using SDR mode. */
FLEXSPI_COMMAND_RADDR_SDR = 0x02U, /*!< Transmit Row Address to Flash, using SDR mode. */
FLEXSPI_COMMAND_CADDR_SDR = 0x03U, /*!< Transmit Column Address to Flash, using SDR mode. */
FLEXSPI_COMMAND_MODE1_SDR = 0x04U, /*!< Transmit 1-bit Mode bits to Flash, using SDR mode. */
FLEXSPI_COMMAND_MODE2_SDR = 0x05U, /*!< Transmit 2-bit Mode bits to Flash, using SDR mode. */
FLEXSPI_COMMAND_MODE4_SDR = 0x06U, /*!< Transmit 4-bit Mode bits to Flash, using SDR mode. */
FLEXSPI_COMMAND_MODE8_SDR = 0x07U, /*!< Transmit 8-bit Mode bits to Flash, using SDR mode. */
FLEXSPI_COMMAND_WRITE_SDR = 0x08U, /*!< Transmit Programming Data to Flash, using SDR mode. */
FLEXSPI_COMMAND_READ_SDR = 0x09U, /*!< Receive Read Data from Flash, using SDR mode. */
FLEXSPI_COMMAND_LEARN_SDR = 0x0AU, /*!< Receive Read Data or Preamble bit from Flash, SDR mode.
*/
FLEXSPI_COMMAND_DATSZ_SDR = 0x0BU, /*!< Transmit Read/Program Data size (byte) to Flash, SDR
mode. */
kFLEXSPI_Command_DUMMY_SDR = 0x0CU, /*!< Leave data lines undriven by FlexSPI controller.*/
kFLEXSPI_Command_DUMMY_RWDS_SDR = 0x0DU, /*!< Leave data lines undriven by FlexSPI controller,
* dummy cycles decided by RWDS. */
kFLEXSPI_Command_DDR = 0x21U, /*!< Transmit Command code to Flash, using DDR mode. */
kFLEXSPI_Command_RADDR_DDR = 0x22U, /*!< Transmit Row Address to Flash, using DDR mode. */
kFLEXSPI_Command_CADDR_DDR = 0x23U, /*!< Transmit Column Address to Flash, using DDR mode. */
kFLEXSPI_Command_MODE1_DDR = 0x24U, /*!< Transmit 1-bit Mode bits to Flash, using DDR mode. */
kFLEXSPI_Command_MODE2_DDR = 0x25U, /*!< Transmit 2-bit Mode bits to Flash, using DDR mode. */
kFLEXSPI_Command_MODE4_DDR = 0x26U, /*!< Transmit 4-bit Mode bits to Flash, using DDR mode. */
kFLEXSPI_Command_MODE8_DDR = 0x27U, /*!< Transmit 8-bit Mode bits to Flash, using DDR mode. */
kFLEXSPI_Command_WRITE_DDR = 0x28U, /*!< Transmit Programming Data to Flash, using DDR mode. */
kFLEXSPI_Command_READ_DDR = 0x29U, /*!< Receive Read Data from Flash, using DDR mode. */
kFLEXSPI_Command_LEARN_DDR = 0x2AU, /*!< Receive Read Data or Preamble bit from Flash, DDR mode.
*/
kFLEXSPI_Command_DATSZ_DDR = 0x2BU, /*!< Transmit Read/Program Data size (byte) to Flash, DDR
FLEXSPI_COMMAND_DUMMY_SDR = 0x0CU, /*!< Leave data lines undriven by FlexSPI controller.*/
FLEXSPI_COMMAND_DUMMY_RWDS_SDR = 0x0DU, /*!< Leave data lines undriven by FlexSPI controller,
* dummy cycles decided by RWDS. */
FLEXSPI_COMMAND_DDR = 0x21U, /*!< Transmit Command code to Flash, using DDR mode. */
FLEXSPI_COMMAND_RADDR_DDR = 0x22U, /*!< Transmit Row Address to Flash, using DDR mode. */
FLEXSPI_COMMAND_CADDR_DDR = 0x23U, /*!< Transmit Column Address to Flash, using DDR mode. */
FLEXSPI_COMMAND_MODE1_DDR = 0x24U, /*!< Transmit 1-bit Mode bits to Flash, using DDR mode. */
FLEXSPI_COMMAND_MODE2_DDR = 0x25U, /*!< Transmit 2-bit Mode bits to Flash, using DDR mode. */
FLEXSPI_COMMAND_MODE4_DDR = 0x26U, /*!< Transmit 4-bit Mode bits to Flash, using DDR mode. */
FLEXSPI_COMMAND_MODE8_DDR = 0x27U, /*!< Transmit 8-bit Mode bits to Flash, using DDR mode. */
FLEXSPI_COMMAND_WRITE_DDR = 0x28U, /*!< Transmit Programming Data to Flash, using DDR mode. */
FLEXSPI_COMMAND_READ_DDR = 0x29U, /*!< Receive Read Data from Flash, using DDR mode. */
FLEXSPI_COMMAND_LEARN_DDR = 0x2AU, /*!< Receive Read Data or Preamble bit from Flash, DDR mode.
*/
FLEXSPI_COMMAND_DATSZ_DDR = 0x2BU, /*!< Transmit Read/Program Data size (byte) to Flash, DDR
mode. */
kFLEXSPI_Command_DUMMY_DDR = 0x2CU, /*!< Leave data lines undriven by FlexSPI controller.*/
kFLEXSPI_Command_DUMMY_RWDS_DDR = 0x2DU, /*!< Leave data lines undriven by FlexSPI controller,
* dummy cycles decided by RWDS. */
kFLEXSPI_Command_JUMP_ON_CS = 0x1FU, /*!< Stop execution, deassert CS and save operand[7:0] as
* the instruction start pointer for next sequence */
FLEXSPI_COMMAND_DUMMY_DDR = 0x2CU, /*!< Leave data lines undriven by FlexSPI controller.*/
FLEXSPI_COMMAND_DUMMY_RWDS_DDR = 0x2DU, /*!< Leave data lines undriven by FlexSPI controller,
* dummy cycles decided by RWDS. */
FLEXSPI_COMMAND_JUMP_ON_CS = 0x1FU, /*!< Stop execution, deassert CS and save operand[7:0] as
* the instruction start pointer for next sequence */
};

struct flexspi_core_config
{
uintptr_t base;
const uint32_t *lut;
size_t lut_elements;
};

struct flexspi_nor_config
{
struct flexspi_nor_config {
const char *name;
const uint8_t *uuid;
enum flexspi_port port;
Expand All @@ -122,6 +128,8 @@ struct flexspi_nor_config
uint8_t mfg_capacity;
uint32_t time_block_erase_ms;
uint32_t time_page_program_ms;
uint32_t cr1;
uint32_t cr2;
uint8_t lut_id_read_status;
uint8_t lut_id_read_id;
uint8_t lut_id_erase;
Expand All @@ -131,7 +139,17 @@ struct flexspi_nor_config
uint8_t lut_id_wr_disable;
};

int imx_flexspi_core_init(const struct flexspi_core_config *config);
bio_dev_t imx_flexspi_nor_init(const struct flexspi_nor_config *nor_config);
struct flexspi_core_config {
uintptr_t base;
uint32_t cr4;
uint32_t dllacr;
uint32_t dllbcr;
size_t lut_elements;
const uint32_t *lut;
size_t mem_length;
const struct flexspi_nor_config *mem[];
};

int imx_flexspi_init(const struct flexspi_core_config *config);

#endif // INCLUDE_DRIVERS_MEMC_IMX_FLEXSPI_H
3 changes: 3 additions & 0 deletions include/pb/bio.h
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Original file line number Diff line number Diff line change
Expand Up @@ -163,6 +163,9 @@ int bio_set_ios(bio_dev_t dev, bio_read_t read, bio_write_t write);
*/
int bio_set_ios_erase(bio_dev_t dev, bio_erase_t erase);

int bio_set_private(bio_dev_t dev, uintptr_t priv);
uintptr_t bio_get_private(bio_dev_t dev);

/**
* Block device size in bytes
*
Expand Down
22 changes: 22 additions & 0 deletions src/bio.c
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Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,7 @@ struct bio_device {
bio_write_t write;
bio_erase_t erase;
bio_call_t install_partition_table;
uintptr_t private;
bool valid;
};

Expand Down Expand Up @@ -85,6 +86,7 @@ bio_dev_t bio_allocate_parent(bio_dev_t parent,
bio_pool[new].read = bio_pool[parent].read;
bio_pool[new].write = bio_pool[parent].write;
bio_pool[new].erase = bio_pool[parent].erase;
bio_pool[new].private = bio_pool[parent].private;

return new;
}
Expand Down Expand Up @@ -123,6 +125,26 @@ int bio_set_ios_erase(bio_dev_t dev, bio_erase_t erase)
return PB_OK;
}

int bio_set_private(bio_dev_t dev, uintptr_t priv)
{
int rc;

rc = check_dev(dev);
if (rc != PB_OK)
return rc;

bio_pool[dev].private = priv;

return PB_OK;
}

uintptr_t bio_get_private(bio_dev_t dev)
{
if (check_dev(dev) != PB_OK)
return 0;
return bio_pool[dev].private;
}

int64_t bio_size(bio_dev_t dev)
{
int rc;
Expand Down
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