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PCI: Add MCFG quirks for Tegra194 host controllers
The PCIe controller in Tegra194 SoC is not completely ECAM-compliant. With the current hardware design limitations in place, ECAM can be enabled only for one controller (C5 controller to be precise) with bus numbers starting from 160 instead of 0. A different approach is taken to avoid this abnormal way of enabling ECAM for just one controller but to enable configuration space access for all the other controllers. In this approach, ops are added through MCFG quirk mechanism which access the configuration spaces by dynamically programming iATU (internal AddressTranslation Unit) to generate respective configuration accesses just like the way it is done in DesignWare core sub-system. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> [ Updated by jonathanh@nvidia.com only permit building the Tegra194 PCIe driver into the kernel and not as a module ] Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
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