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Small compiler improvement: compile LWL, LWR, SWL and SWR MIPS
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instructions
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@gid15
gid15 committed May 25, 2019
1 parent 0858ea2 commit 7136396
Showing 1 changed file with 108 additions and 4 deletions.
112 changes: 108 additions & 4 deletions src/jpcsp/Allegrex/Instructions.java
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Expand Up @@ -4182,7 +4182,33 @@ public void interpret(Processor processor, int insn) {
}
@Override
public void compile(ICompilerContext context, int insn) {
context.compileRTRSIMM("doLWL", true);
if (!context.isRtRegister0()) {
MethodVisitor mv = context.getMethodVisitor();
int simm16 = context.getImm16(true);
context.prepareRtForStore();
context.memRead32(context.getRsRegisterIndex(), simm16);
context.loadRs();
if (simm16 != 0) {
context.loadImm16(true);
mv.visitInsn(Opcodes.IADD);
}
context.loadImm(0x3);
mv.visitInsn(Opcodes.IAND);
context.loadImm(0x3);
mv.visitInsn(Opcodes.ISHL);
mv.visitInsn(Opcodes.DUP_X1);
context.loadImm(0x3 << 3);
mv.visitInsn(Opcodes.IXOR);
mv.visitInsn(Opcodes.ISHL);
mv.visitInsn(Opcodes.SWAP);
context.loadImm(0x00FFFFFF);
mv.visitInsn(Opcodes.SWAP);
mv.visitInsn(Opcodes.ISHR);
context.loadRt();
mv.visitInsn(Opcodes.IAND);
mv.visitInsn(Opcodes.IOR);
context.storeRt();
}
}
@Override
public String disasm(int address, int insn) {
Expand Down Expand Up @@ -4213,7 +4239,33 @@ public void interpret(Processor processor, int insn) {
}
@Override
public void compile(ICompilerContext context, int insn) {
context.compileRTRSIMM("doLWR", true);
if (!context.isRtRegister0()) {
MethodVisitor mv = context.getMethodVisitor();
int simm16 = context.getImm16(true);
context.prepareRtForStore();
context.memRead32(context.getRsRegisterIndex(), simm16);
context.loadRs();
if (simm16 != 0) {
context.loadImm16(true);
mv.visitInsn(Opcodes.IADD);
}
context.loadImm(0x3);
mv.visitInsn(Opcodes.IAND);
context.loadImm(0x3);
mv.visitInsn(Opcodes.ISHL);
mv.visitInsn(Opcodes.DUP_X1);
mv.visitInsn(Opcodes.IUSHR);
mv.visitInsn(Opcodes.SWAP);
context.loadImm(0xFFFFFF00);
mv.visitInsn(Opcodes.SWAP);
context.loadImm(0x3 << 3);
mv.visitInsn(Opcodes.IXOR);
mv.visitInsn(Opcodes.ISHL);
context.loadRt();
mv.visitInsn(Opcodes.IAND);
mv.visitInsn(Opcodes.IOR);
context.storeRt();
}
}
@Override
public String disasm(int address, int insn) {
Expand Down Expand Up @@ -4402,7 +4454,33 @@ public void interpret(Processor processor, int insn) {
}
@Override
public void compile(ICompilerContext context, int insn) {
context.compileRTRSIMM("doSWL", true);
if (!context.isRtRegister0()) {
MethodVisitor mv = context.getMethodVisitor();
int simm16 = context.getImm16(true);
context.prepareMemWrite32(context.getRsRegisterIndex(), simm16);
context.loadRt();
context.loadRs();
if (simm16 != 0) {
context.loadImm16(true);
mv.visitInsn(Opcodes.IADD);
}
context.loadImm(0x3);
mv.visitInsn(Opcodes.IAND);
context.loadImm(0x3);
mv.visitInsn(Opcodes.ISHL);
mv.visitInsn(Opcodes.DUP_X1);
context.loadImm(0x3 << 3);
mv.visitInsn(Opcodes.IXOR);
mv.visitInsn(Opcodes.IUSHR);
mv.visitInsn(Opcodes.SWAP);
context.loadImm(0xFFFFFF00);
mv.visitInsn(Opcodes.SWAP);
mv.visitInsn(Opcodes.ISHL);
context.memRead32(context.getRsRegisterIndex(), simm16);
mv.visitInsn(Opcodes.IAND);
mv.visitInsn(Opcodes.IOR);
context.memWrite32(context.getRsRegisterIndex(), simm16);
}
}
@Override
public String disasm(int address, int insn) {
Expand Down Expand Up @@ -4433,7 +4511,33 @@ public void interpret(Processor processor, int insn) {
}
@Override
public void compile(ICompilerContext context, int insn) {
context.compileRTRSIMM("doSWR", true);
if (!context.isRtRegister0()) {
MethodVisitor mv = context.getMethodVisitor();
int simm16 = context.getImm16(true);
context.prepareMemWrite32(context.getRsRegisterIndex(), simm16);
context.loadRt();
context.loadRs();
if (simm16 != 0) {
context.loadImm16(true);
mv.visitInsn(Opcodes.IADD);
}
context.loadImm(0x3);
mv.visitInsn(Opcodes.IAND);
context.loadImm(0x3);
mv.visitInsn(Opcodes.ISHL);
mv.visitInsn(Opcodes.DUP_X1);
mv.visitInsn(Opcodes.ISHL);
mv.visitInsn(Opcodes.SWAP);
context.loadImm(0x3 << 3);
mv.visitInsn(Opcodes.IXOR);
context.loadImm(0x00FFFFFF);
mv.visitInsn(Opcodes.SWAP);
mv.visitInsn(Opcodes.ISHR);
context.memRead32(context.getRsRegisterIndex(), simm16);
mv.visitInsn(Opcodes.IAND);
mv.visitInsn(Opcodes.IOR);
context.memWrite32(context.getRsRegisterIndex(), simm16);
}
}
@Override
public String disasm(int address, int insn) {
Expand Down

2 comments on commit 7136396

@sum2012
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@sum2012 sum2012 commented on 7136396 Nov 8, 2020

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Break Downstream Panic! - ULUS10322
http://www.emunewz.net/forum/showthread.php?tid=41262&pid=365312#pid365312

@sum2012
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@sum2012 sum2012 commented on 7136396 Nov 9, 2020

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fix in
97124eb

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