Converting System Verilog to plain Verilog using .xml dump from Verilator
This software takes a dump .xml file generated by Verilator using the --xml-only option and parses it using the xml-light library to reproduce the original syntax (using an optimised and simplified representation) that will hopefully (in the sense of we hope it will be useful) be more portable between different tools, and in particular support out-of-context synthesis.
INSTALLATION
This package requires Verilator to be installed (at earliest git master version towards 4.010), or else the patched version here (https://github.com/jrrk/verilator.git).
opam must be installed and updated, and the following version was tested:
opam switch 4.04.0
eval `opam config env`
eval `opam config env`
opam install xml-light
make vxml
OPERATION
The System Verilog to be tested must first be converted to XML using (typically):
verilator --xml-only -Wno-fatal "verilog files ..."
The output will be generated by default in obj_dir/something.xml
where the name something depends on the toplevel you asked for and the source file name(s)
For debugging the package runs in the toplevel REPL.
Edit .ocamlinit appropriately, then
./vxml
alternatively:
./vxmlmain obj_dir/something.xml
ENVIRONMENT
The following environment variables are effective:
export XMLSRCPATH="." path to verilator run directory if different from current directory export VXML_SEPARATE=1 each output module is in a separate .v file (default true) export VXML_DEBUGTREE=1 produce copious debugging information in side files (default true) export VXML_OPTTREE=1 generate _opt.v files which remove interfaces, otherwise just parameters and enums etc. will be removed