Gowin FPGA Code Generators

This repository contains interactive code generators for Gowin FPGAs. They are basically a reimplementation of the same features found under the Tools.. -> IP Core Generator, but tailored to fit my own use.

Visit here for the live page.

PLL calculator

The file pll_calculator.html contains a Verilog PLL code generator.

Timing constraints visualizer

The file timing_constraints.html contains a visualizer for setting up timing constraints for an external data signal.