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Welcome to Final project for "Reti logiche" exam 👋

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At the end of the course the design and implementation in VHDL of a hardware device for the resolution of a given problem was assigned. The description of the course mentions: "The course aims to lead students to the logical design of digital systems, introducing problems and solution methodologies. To this end, the problem of logical synthesis and its optimization will be tackled, starting from the simplest systems - combinatorial ones - to move on to the more complex sequential systems, defining the figures of merit against which the optimization of the synthesis and the techniques on which the automatic design tools are based. Finally, considering the prototyping and / or implementation phase of digital systems, issues related to the use of programmable logic devices (FPGAs) will be considered."

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👤 Juri Sacchetta

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