Jeffrey Young - Research Preprints

Publications and Presentations by Dr. Jeffrey Young, currently a research scientist at Georgia Tech.

All conference proceedings are published here in pre-print format and are provided for personal use by the authors. All other copyrights remain with their respective owners.

2023

Presenter	Title	Publication Type	Date	Venue	Publication Links
Aaron Jezghani	"The Rogues Gallery: A Novel Architecture Testbed!"	Presentation	3/21/23	NSF Access Campus Champions Meeting	[Slides]
Aaron Jezghani	"Future Computing with the Rogues Gallery"	Paper	TBD	EduPar 2023, IPDPS	[Slides TBD] [Paper] [Abstract]

Future Computing with the Rogues Gallery

Authors: Aaron Jezghani, Jeffrey Young, Will Powell, Ronald Rahaman, J. Eric Coulter

The Vertically Integrated Projects (VIP) Program at Georgia Tech provides a multidisciplinary research experience aimed at engaging undergraduate and graduate research students in large-scale computing research projects. Since 2019, the Future Computing with the Rogues Gallery VIP course has engaged over 75 students in research on topics related to novel architectures and "post-Moore" computing platforms built around quantum, neuromorphic, near-memory, and reconfigurable computing.

One of the key takeaways from this course for the course designers has been on the correlation between these novel computing platforms and traditional skills, techniques, and tools that are used in the HPC and parallel computing arenas. We discuss these parallels as well as the impacts of this course on general student success and research outcomes.

2022

Presenter	Title	Publication Type	Date	Venue	Publication Links
Jeffrey Young	"Enhancing HPC Education and Workflows with Novel Computing Architectures"	Paper	6/11/22	PEARC 2022, SEHET	[Slides] [Paper] [Abstract]
Jeffrey Young	"Rogues Gallery Spring 2022 Updates"	Presentation	3/9/22	Georgia Tech	[Slides] [Video]
Aaron Jezghani	"Jupyter-based Self-Service Training in OOD for Novel Computing Architectures"	Presentation	2/10/22	OOD Users Forum	[Slides]
Aaron Jezghani	"Onboarding Users to A64FX via Open OnDemand"	Paper	1/14/22	IWAHPCE 2022	[Slides] [Paper] [Abstract]

Enhancing HPC Education and Workflows with Novel Computing Architectures

Authors: Jeffrey Young, Aaron Jezghani, Jeffrey Valdez, Sam Jijina, Xueyang Liu, William Powell, Michael D. Weiner, Semir Sarajlic

Recent HPC education efforts have focused on maximizing the usage of traditional- and cloud-based computing infrastructures that primarily support CPU or GPU hardware. However, recent innovations in CPU architectures from Arm and RISC-V and the acquisition of Field-Programmable Gate Array (FPGA) companies by vendors like Intel and AMD mean that traditional HPC clusters are rapidly becoming more heterogeneous.

This work investigates one such example deployed at Georgia Tech - a joint workflow for processor design and reconfigurable computing courses supported by both the HPC-focused Partnership for an Advanced Computing Environment (PACE) and GT's novel architecture center, CRNCH. This collaborative workflow of HPC nodes and 40 remotely accessible Pynq devices supported over 100 students in Spring 2022, and its deployment provides key lessons on sticking points and opportunities for combined HPC and novel architecture workflows.

Onboarding Users to A64FX via Open OnDemand

Authors: Aaron Jezghani, Kevin Manalo, William Powell, Jeffrey Valdez, Jeffrey Young

Arm HPC has succeeded in scaling up in the supercomputing space with the deployment of systems like RIKEN's Fugaku supercomputer and Sandia's Astra cluster. At the same time, the onboarding of new users to the Arm HPC ecosystem has never been more complex due to an overabundance of compilers, libraries, and build options for tools and applications.

This work investigates one particular method to ease the integration of new users into the space of Arm HPC through the use of OOD to provide a consistent and easy-to-use front-end for Georgia Tech's A64FX cluster, Octavius. We detail the motivations for this deployment as well as the potential pitfalls in integrating with an Arm A64FX environment. User-motived applications that incorporate the interactive usage of virtual desktops and Jupyter notebooks are discussed as motivating user workflows, and we provide some context on how future deployments might look with combined Arm and OOD integration.

2021

Presenter	Title	Publication Type	Date	Venue	Publication Links
Jeffrey Young	"Rogues Gallery 2021 Updates"	Presentation	1/28/2021	CRNCH Summit 2021	[Slides]

2020

Presenter	Title	Publication Type	Date	Venue	Publication Links
Jason Riedy	"Rogues Gallery and Enabled Research"	Presentation	1/31/2020	CRNCH Summit 2020	[Slides]

2019

Presenter	Title	Publication Type	Date	Venue	Publication Links
Jeffrey Young	"Experimental Insights from the Rogues Gallery"	Paper	11/7/2019	ICRC 2019	[Slides] [Paper] [Abstract]
Jason Riedy	"Wrangling Rogues: A Case Study on Managing Experimental Post-Moore Architectures"	Paper	8/1/2019	PEARC 2019	[Slides] [Paper] [Abstract]

Experimental Insights from the Rogues Gallery

Authors: Jeffrey Young, Jason Riedy, Prasanth Chatarasi, Sriseshan Srikanth, Thomas M. Conte, Vivek Sarkar

The Rogues Gallery is a new deployment for understanding next-generation hardware with a focus on unorthodox and uncommon technologies. This testbed project was initiated in 2017 in response to Rebooting Computing efforts and initiatives. The Gallery's focus is to acquire new and unique hardware (the rogues) from vendors, research labs, and start-ups and to make this hardware widely available to students, faculty, and industry collaborators within a managed data center environment. By exposing students and researchers to this set of unique hardware, we hope to foster cross-cutting discussions about hardware designs that will drive future performance improvements in computing long after the Moore's Law era of cheap transistors ends. We have defined an initial vision of the infrastructure and driving engineering challenges for such a testbed in a separate document, so here we present highlights of the first one to two years of post-Moore era research with the Rogues Gallery and give an indication of where we see future growth for this testbed and related efforts.

Wrangling Rogues: A Case Study on Managing Experimental Post-Moore Architectures

Authors: Will Powell, Jason Riedy, Jeffrey S. Young, Thomas M. Conte

The Rogues Gallery is a new experimental testbed that is focused on tackling "rogue" architectures for the Post-Moore era of computing. While some of these devices have roots in the embedded and high-performance computing spaces, managing current and emerging technologies provides a challenge for system administration that are not always foreseen in traditional data center environments.

We present an overview of the motivations and design of the initial Rogues Gallery testbed and cover some of the unique challenges that we have seen and foresee with upcoming hardware prototypes for future post-Moore research. Specifically, we cover the networking, identity management, scheduling of resources, and tools and sensor access aspects of the Rogues Gallery and techniques we have developed to manage these new platforms.

2016

Presenter	Title	Publication Type	Date	Venue	Publication Links
Jeffrey Young	"Finding Balance in the post-Moore’s Law Era"	Paper	11/15/2016	PMES 2016	[Paper] [Abstract]

Finding Balance in the post-Moore’s Law Era

Authors: Jeffrey Young, Richard Vuduc

Recent developments in 3D stacked memory technologies and the promise of fast optical interconnects have offered new possibilities for balancing communication and computation time in future supercomputers. However, the end of Moore’s Law means that future architectural improvements will become more limited in scope. We theoretically evaluate a proposal that balanced “post-Moore’s” systems will be most achievable via a combination of small, lightweight processors, high-bandwidth memories with optimized “horizontal” communication, and network-oriented algorithm codesign.