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Single-cycle datapath implemented in Verilog with new complex instructions

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kadirhzrc/single-cycle-datapath-with-complex-instructions

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Report.docx

Report.docx

 
 

adder.v

adder.v

 
 

alu32.v

alu32.v

 
 

alucont.v

alucont.v

 
 

control.v

control.v

 
 

mult2_to_1_1.v

mult2_to_1_1.v

 
 

mult2_to_1_32.v

mult2_to_1_32.v

 
 

mult2_to_1_5.v

mult2_to_1_5.v

 
 

our_instructions.pdf

our_instructions.pdf

 
 

processor.v

processor.v

 
 

shift.v

shift.v

 
 

shift_26.v

shift_26.v

 
 

signext.v

signext.v

 
 

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Single-cycle datapath implemented in Verilog with new complex instructions

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