MIPS-MultiCycle

A Multi Cycle implementation of MIPS

How it works ?

This CPU has a 12bit data bus and a 12bit address bus. All of the Instructions are 12 bit. This CPU have these components :

This CPU has 3 groups of Instructions.

Group 0 Instructions :

Instruction Mnemonic	Definition	Bits 11:9	RTL Notation
AND	Logical AND	0	ACC <- ACC & (EA);
ADD	2's complement add	001	{CY, ACC} <- ACC + (EA);
ISZ	Increment and skip if 0	010	(EA) <- (EA) + 1; if (EA) + 1 = 0 skip the next instruction
DCA	Deposit and clear ACC	011	(EA) <- ACC; ACC <- 0;
JMP	Jump	100	Jump to location EA
JMS	Jump to subroutine	101	Jump to subroutine at location EA

Name		Name	Last commit message	Last commit date
Latest commit History 16 Commits
ACC.sv		ACC.sv
ALU.sv		ALU.sv
ALUOut.sv		ALUOut.sv
CY.sv		CY.sv
CarryOut.v		CarryOut.v
DataPath.sv		DataPath.sv
EA.sv		EA.sv
IR.sv		IR.sv
MDR.sv		MDR.sv
PC.sv		PC.sv
README.md		README.md
TB.sv		TB.sv
controller.sv		controller.sv
memory.sv		memory.sv
mipsMulti.sv		mipsMulti.sv
mux.sv		mux.sv