This repository contains SystemVerilog code examples aimed at illustrating various verification techniques. The examples are sourced from three main references:
- "SystemVerilog for Verification: A Guide to Learning the Testbench Language Features"
- Dr. Ayman Wahba Lectures
- Additionally, I've added my contributions and explanations to enhance the educational value of each example.
- Data Types:
- Overview of built-in data types, including arrays and queues.
- Explanation of dynamic arrays, associative arrays, and linked lists.
- Utilizing array methods and choosing appropriate storage types.
- Creating user-defined structures, enumerated types, and constants.
- Understanding strings, expression width, and net types.
- Procedural Statements and Routines:
- Overview of procedural statements, tasks, functions, and void functions.
- Handling routine arguments, local data storage, and time values.
- Practical examples and best practices for procedural programming.
- Basic OOP:
- Introduction to object-oriented programming (OOP) concepts.
- Creating and using classes, objects, and routines.
- Understanding scoping rules, dynamic objects, and object deallocation.
- Exploring public vs. private access, static vs. global variables, and class inheritance.
- Connecting the Testbench and Design:
- Separating testbench and design, utilizing the interface construct.
- Managing stimulus timing, driving, and sampling.
- Integrating assertions, program-module interactions, and top-level scope.
- Randomization:
- Techniques and best practices for effective randomization.
- Constraint-based randomization, solution probabilities, and controlling constraints.
- Handling common randomization problems and advanced randomization techniques.
- Threads and Interprocess Communication:
- Working with threads, interprocess communication (IPC), events, semaphores, and mailboxes.
- Building test benches using threads and IPC for concurrent execution.
- Advanced OOP and Guidelines:
- Exploring advanced OOP concepts such as inheritance, factory patterns, and type casting.
- Understanding composition, alternatives to inheritance, and callbacks.
- Functional Coverage:
- Strategies for implementing functional coverage in verification.
- Anatomy of cover groups, triggering, data sampling, and cross coverage.
- Parameterized cover groups, and coverage options, and analyzed coverage data.
- Advanced Interfaces:
- Utilizing virtual interfaces, connecting to multiple design configurations, and procedural code in interfaces.
- Clone the repository to your local machine.
- Navigate to the desired example directory.
- Open the code files using a SystemVerilog-compatible editor or Integrated Development Environment (IDE).
- Read through the code and accompanying documentation to understand the concepts being illustrated.
- Simulate the examples using a SystemVerilog simulator to observe their behavior and verify their correctness.
The code examples in this repository are provided under the MIT License. Please refer to the LICENSE file for more details.
Karim Mahmoud |