draft: f3: adc: drop the need for extsel defines

Note: this is "compatible" with prior f3 code, but is completely different
behaviour to f4 for instance, so would be surprising and bad to make the change
as is.  it's just an idea.  This would however completley drop the idea of
tryign to make defines that cover all the complicated f3 cases.

Relates to github issue libopencm3#518

include/libopencm3/stm32/f3/adc.h

@@ -438,24 +438,26 @@
 #define ADC_CFGR_EXTEN_MASK		(0x3 << 10)
 
 /* EXTSEL[3:0]: External trigger selection for regular group */
-#define ADC_CFGR_EXTSEL_EVENT_0		(0x0 << 6)
-#define ADC_CFGR_EXTSEL_EVENT_1		(0x1 << 6)
-#define ADC_CFGR_EXTSEL_EVENT_2		(0x2 << 6)
-#define ADC_CFGR_EXTSEL_EVENT_3		(0x3 << 6)
-#define ADC_CFGR_EXTSEL_EVENT_4		(0x4 << 6)
-#define ADC_CFGR_EXTSEL_EVENT_5		(0x5 << 6)
-#define ADC_CFGR_EXTSEL_EVENT_6		(0x6 << 6)
-#define ADC_CFGR_EXTSEL_EVENT_7		(0x7 << 6)
-#define ADC_CFGR_EXTSEL_EVENT_8		(0x8 << 6)
-#define ADC_CFGR_EXTSEL_EVENT_9		(0x9 << 6)
-#define ADC_CFGR_EXTSEL_EVENT_10	(0xA << 6)
-#define ADC_CFGR_EXTSEL_EVENT_11	(0xB << 6)
-#define ADC_CFGR_EXTSEL_EVENT_12	(0xC << 6)
-#define ADC_CFGR_EXTSEL_EVENT_13	(0xD << 6)
-#define ADC_CFGR_EXTSEL_EVENT_14	(0xE << 6)
-#define ADC_CFGR_EXTSEL_EVENT_15	(0xF << 6)
-
-#define ADC_CFGR_EXTSEL_MASK		(0xF << 6)
+/** Don't use these, only here for compatibility.... */
+#define ADC_CFGR_EXTSEL_EVENT_0		0
+#define ADC_CFGR_EXTSEL_EVENT_1		1
+#define ADC_CFGR_EXTSEL_EVENT_2		2
+#define ADC_CFGR_EXTSEL_EVENT_3		3
+#define ADC_CFGR_EXTSEL_EVENT_4		4
+#define ADC_CFGR_EXTSEL_EVENT_5		5
+#define ADC_CFGR_EXTSEL_EVENT_6		6
+#define ADC_CFGR_EXTSEL_EVENT_7		7
+#define ADC_CFGR_EXTSEL_EVENT_8		8
+#define ADC_CFGR_EXTSEL_EVENT_9		9
+#define ADC_CFGR_EXTSEL_EVENT_10	10
+#define ADC_CFGR_EXTSEL_EVENT_11	11
+#define ADC_CFGR_EXTSEL_EVENT_12	12
+#define ADC_CFGR_EXTSEL_EVENT_13	13
+#define ADC_CFGR_EXTSEL_EVENT_14	14
+#define ADC_CFGR_EXTSEL_EVENT_15	15
+
+#define ADC_CFGR_EXTSEL_SHIFT		6
+#define ADC_CFGR_EXTSEL_MASK		0xF
 
 /* ALIGN: Data alignment */
 #define ADC_CFGR_ALIGN		(1 << 5)

lib/stm32/f3/adc.c

@@ -963,7 +963,7 @@ void adc_set_multi_mode(uint32_t mode)
  *
  * @param[in] adc Unsigned int32. ADC block register address base @ref
  * adc_reg_base
- * @param[in] trigger Unsigned int32. Trigger identifier
+ * @param[in] trigger Unsigned int32. Trigger identifier (logical, 0..15)
  * @ref adc_trigger_regular
  * @param[in] polarity Unsigned int32. Trigger polarity @ref
  * adc_trigger_polarity_regular
@@ -974,8 +974,8 @@ void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger,
 {
 	uint32_t reg32 = ADC_CFGR(adc);
 
-	reg32 &= ~(ADC_CFGR_EXTSEL_MASK | ADC_CFGR_EXTEN_MASK);
-	reg32 |= (trigger | polarity);
+	reg32 &= ~((ADC_CFGR_EXTSEL_MASK << ADC_CFGR_EXTSEL_SHIFT) | ADC_CFGR_EXTEN_MASK);
+	reg32 |= (trigger << ADC_CFGR_EXTSEL_SHIFT| polarity);
 	ADC_CFGR(adc) = reg32;
 }