- Day-1: Inception of open-source EDA, OpenLANE and Sky130 PDK
- Day-2: Good FloorPlan Vs Bad FloorPlan and Introduction to Library Cells
- Day-3: Design library cell using Magic Layout and ngspice characterization
- Inception of Layout and CMOS fabrication process
- Sky130 Tech File Labs
- Lab Steps to create final SPICE deck using Sky130tech
- Lab Steps to characterize the Inverter using sky130 model files
- Lab Introduction to Sky130 pdk's and steps to download labs
- Lab Introduction to Magic and steps to load Sky130 tech-rules
- Lab exercise to fix Poly-9 error in Sky130 tech file
- Lab challenge exercise to describe DRC error as geometrical construct
- Lab challenge to find missing or Incorrect rules and fix them
- Day-4: Pre-layout timing analysis and importance of good clock tree
- Day-5: Final steps for RTL2GDS using tritonRoute and openSTA
Aurdino Board: The image below is an Aurdino Microcontroller Board. Here we focus more on the encircled area, which contains the 'Microprocessor',that we will be designing from abstract level till fabrication level by using RTL to GDS flow
While we cosider the chip, there are 3 main components:
(1) Pads : Through these pads signals can travel into the chip from external sources and viceversa.
(2) Die : It is the whole area of the chip that will be manufactured on the silicon wafer.
(3) Core : It is the area where our entire logic will be implemented.
The above mentioned MicroProcessor in an aurdino board is a package that consists of MicroProcessor chip and some other Foundry IP's(Intellectual Property). All of these combined called as a package.
For example, let's consider a package that consists of RISC V SOC and some other IP's such as SRAM , ADC , DAC , PLL etc..
ISA: ISA is known as "Instruction Set Architecture". It is nothing but a way of communicating with the computer. In general we write codes that need to be executed by the system, using coding languages like C , Java etc. , but machine can't understand those languages. It is where ISA comes into picture. By using ISA the codes that were written wil be converted into assembly language and from there to binary i.e Machine understandable language. This is the purpose of the ISA, and the RISC V ISA is the latest ISA released.
In real life we generally deal with Application Softwares(Apps) in order to communicate with the Hardware.But how it's done exactly? In between Application software and Hardware, there will be a software called System Software. The Applications enter into the System Software and will be converted into the Hardware understandable language i.e Binary Language.
The System Software consists of different layers:
(1) O.S : Other than the general operations like Handling I.O operations, Allocating Memory, Low level System Functions the O.S converts the Application software to respected C,C++,Java etc.. codes.
(2) Compiler : The compiler takes output of O.S as input and converts the codes in C,C++,Java etc.. into Instruction set(.exe files). These instructions will be dependent on type of hardware used.
(3) Assembler : Assembler converts the .exe files into binary language and provides it to the hardware, and hardware performs the respective operations.
In order to design a Open Source Digital ASIC, we primarily need some components. Such as
(1) RTL Designs
(2) EDA Tools
(3) PDK Data
There are some open sources to get these required components.
For example, In case of RTL Designs we have librecores.org , opencores.org , github.com etc...
In case of EDA Tools we have Qflow , OpenRoad , OpenLane etc...
In case of PDK Data, Recently in 2020 Google collabarated with SkyWater Technology and made FOSS 130nm Production PDK OpenSource.
What are RTL Designs?
RTL(Register-Transfer-Level) design is a crucial step in the VLSI design flow, which involves the creation of electronic circuits using integrated circuits (ICs). It involves the specification of a digital circuit in terms of the flow of digital signals between hardware registers, and the logical operations performed on those signals.
What are EDA Tools?
EDA(Electronic Design Automation) Tools are used to design and verify the functionality of an Integrated Circuit to ensure it deliver's the required performance and density.
What is PDK Data?
PDK(Process Design Kit) is a collection of files used to model a fabrication process for EDA Tools used in the design of an IC.The collection consists of
- Process Design Rules : DRC , LVS , PEX
- Device Models
- Digital Standard Cell Libraries
- I/O Libraries etc....
The simplified RTL to GDS Flow starts with an RTL file. After going through some set of stages we will get the output as a GDS file, which can be readily sent to foundry for fabrication. The steps involved in the RTL2GDS Flow is of following:
(1) synthesis :
- In synthesis stage RTL file will be converted into a circuit by using the components from the Standard Cell Library.
- The cells in the Standard Cell Library are called Standard Cells and they have the regular layout of same height but different widths.
- Each cell has different models based on Electrical,HDL,Spice,Layout(Abstract and Detailed) etc....
(2) Floor Planning & Power Planning :
- Floor Planning is a stage where the position of the components on the chip will be decided by keeping the area of the chip as minimal as possible by following a set of rules.
- During the Floor Planning Stage itself the position of I/O pins,ports,pads will be determined.
- In Power Planning stage the Power supply network i.e VDD & GND of the chip will be laid out. During Power PLanning 3 components Power Rings , Power Straps , Power Pads will be laid out.
- For Power Network Top Metal Layers will be used because the Power Network should have minimum delay as possible and the top layers of metal will have the low resistance, So they are used.
(3) Placement :
- In Placement stage the components are placed within the areas planned during the FloorPlanning Stage.
- Along with them Standard Cells that are required in the design are also placed within the cell boundaries.
- Placement will be performed in 2 stages. They are Global Placement and Detailed Placement.
- During Global Placement the Standard cells may overlap and does not follow the Placement Rules.
- In Detailed Placement every standard cell will be placed in its optimal position by following the Placement rules.
(4) CTS(Clock Tree Synthesis) :
- Before Performing Routing of the signals, we should perform Clock Routing.
- While Routing the clock tha major problem is CLock Skew.
- Clock Skew is the difference in time taken for the clock to reach two different destinations in the design.
- In order to eliminate the clock skew, we should deploy the technique called Symmetric Tree Structure.
- There are different types of Symmetric Tree Structures. They are H-tree,I-tree,X-tree etc...
(5) Routing :
- Afetr the clock routing is done, now signals must be routed.
- Router uses the remaining metal layers and makes conections in the design.
- Routing will be carried out in 2 stages.They are Global Routing and Detailed Routinng.
- In the stage of Global Routing, the tool generates a Routing guide by following the instructions given in the PDK.
- In the stage of Detailed Routing, actual routing will be done according to the guide generated in the Global Routing Stage.
(6) Sign-off :
- After Routing is done, the chip will be considered as completed and during Sign-off stage different types of checks will be performed.
- Physical Verification Checks : Design Rule Check(DRC) , Layout Vs Schematic(LVS)
- In DRC, the chip will be verified for the violations in the Design Rules provided by the PDK.
- In LVS, the chip will be checked for the functionality whether it matches to the gate level netlist functinality.
- Timing Checks : Static Timing Analysis(STA)
- During STA, the design is checked for Timing violations.
OpenLane is started as an Open Source Flow for a true Open Source Tape-out experiment.It was from e-fabless.It is a platform which supports different tools such as Yosys,OpenRoad,Magic,KLlayout and some other Open source tools.It integrates the various steps of Silicon Implementation and abstracts it. At e-fabless they have an SOC family called Strive. Strive is a family of open everything SOCs having Open PDK, Open RTL, Open EDA.
The Strive SOC family of several members and the list is given below
The main goal of OpenLane is to "Produce a clean GDS file with no human intervention with no LVS,DRC,Timing violations. It is majorly tuned for Skywater 130nm OpenPDK but also supports XFab180 and GF130G. It is functional out of the box.It can be used Harden Macros and chips. It has two modes of operation , autonomous and interactive. It has a feauture called Design Space Exploration which helps in finding the best set of flow configurations.Presently it also has large no.of design examples nearly 43 and more will be added soon.
The image shows the OpenLane detailed ASIC Design Flow.The flow starts with Design RTL, It goes through RTL synthesis by Yosys and abc giving an optimised gate level netlist. Now we perform STA on the optimised netlist inorder to check for Timing violations. After STA we perofrm DFT and this step is optional and for this we use FAULT tool.
Fault(for DFT) :
- Scan Insertion
- Automatic Test Pattern Generation(ATPG)
- Test Pattern Compaction
- Fault coverage
- Fault Simulation
After performing DFT next comes Physical Implementation.It is also called as Automated PnR(Place and Route) and for this we use OpenRoad.
OpenRoad(for Physical Implementation) :
- Floor/Power Planning
- End Decoupling Capacitors and Tap Cells Insertion
- Placement: Global and Detailed
- Post placement optimization
- Clock Tree Synthesis
- Routing: Global and Detailed
During PnR for every change in the design, we should check for LEC(Logic Equivalance Checking). LEC is used to confirm that the function did not change after modifying the netlist and also during physical implementation we have a important step called "Fake Antenna Diodes Insertion Script".
Dealing with Antenna Rule violations : When a metal wire segment is fabricated, it can act as an antenna.
- Reactive ion etching causes charge to accumilate on the wire.
- Transistor gates can be damaged during fabrication.
There are two solutions for this problem
- Bridging attaches a higher layer intermediary. It requires Router awareness.
- Add antenna diode cell to leak away the charges. Antenna diodes are provided by the SCL. For this we took a preventive approach.
- Add a Fake antenna didoe next to every cell input after placement.
- Run the Antenna Checker(Magic) on the routed layout.
- If the checker reports violation on the cell input pin, replace the fake diode cell by a real one
And at the end, we perform Physical Verification. Which includes DRC(Design Rule Checking) , LVS(Layout Vs Schematic). Along with the P.V we also performs STA to check for timing violations in the design.
- MAGIC is used for DRC and SPICE Extraction from Layout.
- MAGIC and Netgen are used for LVS by comparing Extracted SPICE by MAGIC and Verilog Netlist.
In order to access the OpenLane tool, we will be needing some basic linux commands.They are listed below
- pwd : It displays the present working directory and its path.
- cd : Using this command we can move in both ways in the directory tree.
- ls : It lists all the sub-directories and files present in the current directory.
- mkdir : Using this command, we can create a new directory.
- rmdir : Using his command, we can delete an existing directory.
- rm : This command is used to delete the files.
- help : using this command we can know the working of any command.
- clear : This command clears the terminal.
In order to enter into BASH, by being in OpenLane directory we should use a command called docker. By using docker command we will enter into the Bash. After entering into bash we have to use the script flow.tcl, because this .tcl file contains the steps that need to be executed in the OpenLane and along with the tcl file we need to use -interactive switch in order to perform step by step process. If not used interactive switch the whole flow i.e RTL to GDS will be executed once and the final report will be given. The command that we should use for this is ./flow.tcl -interactive.Now OpenLane is opened and we can observe the change in prompt and now we have to input packages required to run the flow and for this we use the command package require openlane 0.9.
Now we need to select the design on which we are going to perform RTL to GDS flow, we will be having 30 to 40 designs that are pre-built in the design folder in openlane and we will be selecting "picorv32a.v" design for this project.Now in order to perform synthesis(first stage of the project) on this design, first we need to setup the design and for that the command will be prep -design picorv32a.
At the end of the terminal we can see that Preparation is complete.
After Preparation is done a directory with current date will be created in the runs folder.And in that directory all the directorys that are needed to store the results , reports etc.. will be created.
Initially every directory will be empty because we haven't performed any operations on the design.But we will have a direcrory named tmp and it contains different types of files.One of the files will be "merged.lef" file, it contains metal layer level and cell level information.
Now, it's time to proceed with the first step in the project. we need to perform Synthesis on the design. For this we need to use the command run_synthesis.Tool will take some time to perform synthesis, when completed it displays the Synthesis was successful message.
Now we need to find out the flipflop percentage in total cells. For this we use reports from Synthesis stage.
In the above image,we can see that the total no.of cells used in the design are 14876 and the count of D-flipflops in the design are 1613. So, the flipflop percentage is calculated as
**Flop Ratio = ((no.of flipflops) / (Total no.of cells))100 = (1613/14876)100 = 10.84%
Before Performing Synthesis the reports directory was empty. After Synthesis the reports that are generated during synthesis will be stored in the reports directory.
In order to find out the Utilization Factor and Aspect Ratio, first we need to know how to define height and width of core and die areas.
- Core is an area in a chip which is used to place all the logic cells and components in a chip. It is the place where logic lies in a chip.
- Die is an area that encircles the core area and used for placing I/O related components.
The height and width of core area will be decided by the netlist of the design. It will be based on the no.of components required in order to execute the logic and the height and width of the die area will be dependent on the core area height and width.
For example, lets consider a netlist that is having two logic gates and two flipflops each having area of 1 sq.unit. The netlist contains 4 elements and the minimum total area required for the core area will be 4 sq.units.
Utilization Factor : Utilization Factor is defined as "The ratio of the core area occupied by the netlist to the total core area".For a good FloorPlan, The Utilization Factor should never be '1' because when the Utilization factor becomes '1' , there will be no place for adding additional logic if needed and it will be considered as a bad FloorPlan.
Utilization Factor = (Area occupied by netlist / Total core area)
Aspect Ratio : Aspect Ratio is defined as "The ratio of Height of the core to the width of the core". If the Aspect ratio is '1' , then the core is said to be in a square shape and other than '1' the core will be a rectangle.
Aspect Ratio = (Height of the core / Width of the core)
Lets consider the above mentioned example and evaluate some cases
In this case, when calculated
- Utilization factor = (4 squnits)/(4 squnits) = 1
- Aspect Ratio = (2 units)/(2 units) = 1 //The core is in a square shape.
In this case, whwn calculated
- Utilization factor = (4 squnits)/(8 squnits) = 0.5
- Aspect Ratio = (2 units)/(4 units) = 0.5 //The core is in a rectangular shape.
In this case , when calculated
- Utilization factor = (4 squnits)/(16 squnits) = 0.25
- Aspect Ratio = (4 units)/(4 units) = 1 //The core is in a square shape.
The concept of pre-placing cells is nothing but reusing already designed blocks by not designing them again and again. The most commonly used pre-placed blocks are Memory , comparators , Mux etc.. , These blocks can be called as Macros (or) I.P's .We need to place these macros very carefully in such a way that if these blocks are more connected to input pins, then we should place these close to those input pins. These should be placed in a way such that the wiring length should be decreased.
The term Pre-placed refers to "Placing those blocks prior to placement stage that is in Floorplan stage. After placing those blocks in Floorplan stage we need to define some placement blockages in order to avoid Placing of other standard cell near to those blocks by the tool during placement stage. By using this pre-placed cells the Time-to-Market can be reduced.
Generally these pre-placed blocks will be high-power draining blocks. In some cases, the power they recieve from the power source will not be sufficient for them to perform switching i.e the signal will not be in the range of its noise margin because there will be a voltage drop in the inter-connecting wires. In this case, the De-coupling Capacitors comes into the picture.
These De-cap cells will be placed near to the blocks that will drain high power. When there is no switching is being performed the De-cap cell will be connected to power source and gets charged to its high level and when the switching is being performed the De-cap cells will be connected to the blocks and the power required for the block will be supplied by the De-cap cell, and when ever the switching stops again the De-cap cell will start to getting charged. This is the working of De-cap cells and these cells plays a crucial role in the circuit design.
In the previous section we used De-cap cells to manage power for different blocks.But Decap cells have some limitations such as Leakage power and increase in the area of chip. To overcome these we use a technique called Powerplanning. In some areas of the chip when there is more switching happening, two tyoes of phenomena can occur
- Voltage drop
- Ground bounce
Voltage drop : When a group of cells are simultaneously switching from 0 to 1, then every cell needs the power and In case the power is supplying from one source, there may occur the shotage of power and drop in the input voltage happens at that place. This is called as "Voltage Drop". The problem occurs only when the voltage level goes below the noise margin.
Ground Bounce : When a group of cells are simultaneoisly switching from 1 to 0, then every cell dumps the power to th ground simultaneously to the same ground pin. In this case the ground instead of being at 0 experiences a short rise in the voltage and this is called as "Ground Bounce".The problem occurs only when the voltage level goes above the noise margin.
In order to avoid these abnormalities, a technique called Power Planning is used. In this technique two different Power mashes are used, one for Vdd and another one for Ground.These meshes are prepared by using top two metal layers because they should have less voltage drop. These meshes will be spread across the design and are connected to multiple sources of Vdd and Ground.
With this technique whenever a cell needs power to switch from 0 to 1, it takes from nearest Vdd layer and if a cell needs to drain the power it will drain it to the nearest Ground Layer.
Pin Placement is one of the crucial step in the design process. Bad pin placement results increase in the length of wire used for connectivity, which inturn results in some adverse affects. Pins should be placed in such a way that the required for connecting them to the blocks should be as less as possible. For example if an input pin is driving two blocks then that pin should be placed near to those two blocks.
Let's consider the below design
For the above design the effective pin placement will look like as follows
In the above pin placement, we can observe two things
- The order of input pins and output pins is random. As already mentioned the pins should be placed based on the connectivity not based on the order.
- The pins used for clock signals are larger in size when compared to pins used for signals, this is because clock is one of the important signal in the design and delays and voltage drops in the clock signal leads to failure of the chip. That is the reason why we use higher metal layers for routing the clock in the design.
After finishing the pin placement, we should use placement blockages outside of the core area and inside of the die area inorder to avoid placement and routing tool using that space for placement and routing, because it is the area dedicated only for Pin Placement purpose.
For Floorplan to run smoothly, as a designer we should take care of some switches, that makes changes to the floorplan when changed. For example Utilization factor and aspect ratio are also part of switches. Designer should cross check these switches before initializing floorplan whether they are alligned with the project or not. Below image shows different types of switches in floorplan stage.
In the OpenLane lowest priority is given to system default(Floorplanning.tcl) and the second highest priority will be given to config.tcl and the highest priority will be given to PDK_varient.tcl for considering the values for switches.
After confirming that all the switches are as per requirement, now we should executr a command run_floorplan , in order to start the floorplan stage.
If any errors occur during the floorplan stage it will display those errors.If it does not display any errors then our floorplan stage has succesfully completed.
After completion of the floorplan we can check the report generated by the tool and check some of the aspects like die area etc.. , but in order to view the design in GUI we should use MAGIC tool.
In order to enter into the MAGIC tool we need to use the command
magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.floorplan.def &
And in GUI floorplan looks like this
While in the GUI, to allign the design to the middle of the screen. First we need to select the whole design by pressing S in the keyboard and then V in the keyboard.
In order to zoom to any particular area first left click the mouse and select the area to zoom and then right click again, and then press Z in the keyboard to zoom in the selected area.
In order to know the details of any cell in the design, just move the cursor to that cell and press S to select the cell and then in the window of tkcon enter the command "what" then it will displey the details of the selected ine.
In the netlist every element has its own shape, for example And gate has a different shape and or gate has a different shape. But in a library every element has only a square or rectangle shape. A Library consists of every elements that can be readily used and also the elements comes with their respective properties such as area, delay etc.. . We will have different versions of the same element with different properties.
In the above picture we have 3 different sets of same elements. The elements which are larger in size are faster but occupies larger area and the smaller set will occupy less area but are slower when compared to larger ones.
During Placement we should definitely consider the estimated wire length and place the cells according to it. Wire length is estimated by calculating the distance from input source of those cells and the distance to the output sinks that are being driven by them.
For above example tool will place the blocks by using the estimated wire length as shown in the below figure
After successful Floorplanning, the next step in the design process is Placement. Placement stage will consist of two stages
- Global Placement - In Global Placement stage tool decides the places for all standard cells in the design.
- Detailed Placement - In Detailed Placement stage the tool places all the standard cells in their designated places and legalization of the Placement will be done. Legalization is nothing but making sure that standard cells are not overlapped on each other in the design and are placed with in the site rows of the design.
In order to start the placement we need to use the command run_placement.
After Placement is done to check whether the cells are placed correctly or not, we need to check GUI and that will be done using MAGIC tool with the following command
magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.placement.def &
We need to extract the spice netlist from the given Inverter from MAGIC Tool inorder to spice simulation in ngspice tool.
First we need to create an extraction file of the inverter. we can do this by using the command extract all in the tkcon window. This will create an extracted file in the vsdstdcelldesign directory.
Next we need to create a spice file using this extracted file to use within the ngspice tool.For this the command will be
ext2spice cthresh 0 rthresh 0, this will not create any new file.
After that use command ext2spice , this will create a spice file in the vsdstdcelldesign directory.
After extracting the SPICE file, we need to update it according to the design.
After that we need to run the SPICE file in the ngspice tool by using the command ngspice sky130_inv.spice
Now we need to verify the plot of output vs time, we need to use the command plot y vs time a
From the plot that we got from ngspice, we need to characterize four parameters of the Inverter.
-
Rise time : It is the time taken for the output waveform to go to 80% of its max value from 20% of its max value.
x0 = 6.16138e-09, y0 = 0.660007
x0 = 6.20366e-09, y0 = 2.64009
From the above values, Rise time = 0.0422 ns
-
Fall time : It is the time taken for the output to fall from 80% of its max value to 20% of its max value.
x0 = 8.04034e-09, y0 = 2.64003
x0 = 8.06818e-09, y0 = 0.659993
From the above values , Fall Time = 0.0278 ns
-
Propogation Delay : It is the time taken for the 50% of transition from 0 to 1 at the output for the 50% transistion from 1 to 0 at the input side.
x0 = 2.18449e-09, y0 = 1.64994
x0 = 2.15e-09, y0 = 1.65011 From the above values , Prop Delay = 0.034 ns
-
Cell Fall Delay : It is the time taken for the 50% of transition from 1 to 0 at the output for the 50% transistion from 0 to 1 at the input side.
x0 = 4.05432e-09, y0 = 1.65
x0 = 4.05001e-09, y0 = 1.65
From the above values , cell fall delay = 0.0043 ns
We have succesfully characterized the Inverter, now we should create a LEF file.
To download the lab files, being in the home directory use the command
wget http://opencircuitdesign.com/open_pdks/archive/drc_tests.tgzNow you have downloaded the zip file. To extract the labs from the zip file use the command
tar xfz drc_tests.tgzIn the downloaded files ,
.magicrcfile serves as the start-up script for MAGIC.
Use the command
magic -d XRto open the Magic tool
Now, select an area in the gui and guide the pointer on to the metal 3 layer and press P. The selected region will be filled with metal 3. Now in tkcon terminal type the command
cif see VIA2, The metal 3 filled area will be filled VIA2 mask.
Now, lets work on the poly.9 file. Load it into the magic tool by using the command load poly.mag in tkcon terminal.
Check for the spacing between Poly resistor and poly in the layout and compare it with the actual value in the Skywater website. In the image below we can clearly see the error in spacing between them. So now lets resolve it
Open the Sky130a.tech file, which is in the drc_tests directory and check for poly.9 keyword and make the changes that are shown in the images below and save it.
Now again load the tech file by using the command tech load sky130A.tech , and again check drc by using command drc check in the tkcon terminal.
Now load nwell.mag file into the magic and check for violations.
In the above layout we have some violations, Open tech file and make changes as shown
After updating the tech file load it again and check for errors
Now after tapping the nwell violations are resolved.
Now to proceed further we will be needing LEF file of the Inverter cell. we need to extract if from the current Inverter cell.
From PNR point of view, while designing standard cell set two things must be considered
- The Input and output ports must lie on the intersection of the Vertical and Horizontal tracks.
- The width of the standard cell should be an odd multiple of the track pitch and height should be an odd multiple of track vertical pitch.
Open the tracks.info file to know more about tracks
In the cell design input and output ports are on the li1 layer.We need to convert the grid into tracks.
Open the tkcon window and give the command for grid according to the track file.
Now we can see that both input and output ports are placed at the intersection of the tracks. Here our second condition also satisfies as 3 boxes are covered between the boundaries.
Now we need to extract the LEF file.First save .mag file by using the command save sky130_vsdinv.mag in the tkcon terminal.
Now open the saved .mag file using the command magic -T sky130A.tch sky130_vsdinv.mag &
Now in the tkcon terminal use the command lef write in order to create a LEF file.
Now we can open the LEF file and go through it.
To proceed futher lets keep all the required files at single place thet is in src directory. First copy the extracted LEF file into src directory.
After LEF file we need to copy the required libraries, here we will have different types of libraries such as fast , slow, typical etc.. , we need to copy all those .lib files to src directory by using cp command.
Now we need to make some changes in the .config file as shown in the image
After that we need to open bash using command docker being in openlane directory. And enter into the open lane and prepare the design as shown in figure. Once preparation is complete we need to use following commands
set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
add_lefs -src $lefs
And now again use the command run_synthesis and check whether it maps our custom vsdinverter or not.
From the above figure we can see that synthesis was succesful and also we have 1554 instances of our vsdinverter. So this stage is successful.
As we completed with synthesis stage, now we need to perform floorplan by using the following commands
init_floorplan
place_io
tap_decap_or
Now as we done with Floorplan stage, we can proceed to placement stage by using the command run_placement
Now after the placement is done,lets check whether the cell that we have created is placed in the design. For this being in the placement directory we should use the command
magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.placement.def &
Clearly we can see that the cell that we have created " sky130_vsdinv" is placed in the design and now lets check whether it is alligned correctly with other cells or not by using the command expand in the tkcon terminal.
Yes,Its perfectly alligned!
Next step is to perform STA on the design. For this first we need to complete the synthesis stage. After synthesis is done some steps need to be followed.
First, we need to create a new file pre_sta.conf in the openlane directory.
After that we need to create another file called my_base.sdc in the src directory which is picorv32a directory.
Now we need to use the command sta pre_sta.conf being in the openlane directory.
We can say that STA is succesful when the slack that we will get equals to that of synthesis stage.
As we can see that Slack is equal to of that we got in synthesis stage. So STA is succesful.
After improving the timing of the design, the previous design should be replaced with improved design by using the command
write_verilog //path of the previous design//
Now the design will get updated with the improved version.
Now we can start working on it, starting with Floorplan by using the same commands that were used before. After succesful completion of Floorplan we should do placement by using the command run_placement.
After placement is done, we can proceed with cts stage. To perform CTS we should use the command run_cts.
After completion of the cts we can observe that in the synthesis results directory a new .cts file is added. The newly added CTS file contains both the previous netlist and also the clock buffers that were added during the cts stage.
To create a database in the openroad, first we need to enter into the openroad by using the command openroad.
After that we need to follow the following list of commands in the openroad
read_lef /openLANE_flow/designs/picorv32a/runs/04-05_21-50/tmp/merged.lef
read_def /openLANE_flow/designs/picorv32a/runs/04-05_21-50/results/cts/picorv32a.cts.def
write_db pico_cts.db
read_db pico_cts.db
read_verilog /openLANE_flow/designs/picorv32a/runs/04-05_21-50/results/synthesis/picorv32a.synthesis_cts.v
read_liberty $::env(LIB_SYNTH_COMPLETE)
read_sdc /openLANE_flow/designs/picorv32a/src/my_base.sdc
set_propagated_clock [all_clocks]
report_checks -path_delay min_max -format full_clock_expanded -digits 4
After all these steps the db will get created and by using the last command we will get a timing report too.
To remove sky130_fd_sc_hd__clkbuf_1 from the list
set ::env(CTS_CLK_BUFFER_LIST) [lreplace $::env(CTS_CLK_BUFFER_LIST) 0 0]
To check the current value of CTS_CLK_BUFFER_LIST
echo $::env(CTS_CLK_BUFFER_LIST)
To check the current value of CURRENT_DEF
echo $::env(CURRENT_DEF)
To set def as placement def
set ::env(CURRENT_DEF) /openLANE_flow/designs/picorv32a/runs/04-05_21-50/results/placement/picorv32a.placement.def
To run cts
run_cts
To check the current value of CTS_CLK_BUFFER_LIST
echo $::env(CTS_CLK_BUFFER_LIST)
We need to follow the similar steps that we have followed earlier in the openroad.
read_lef /openLANE_flow/designs/picorv32a/runs/04-05_21-50/tmp/merged.lef
read_def /openLANE_flow/designs/picorv32a/runs/04-05_21-50/results/cts/picorv32a.cts.def
write_db pico_cts1.db
read_db pico_cts1.db
read_verilog /openLANE_flow/designs/picorv32a/runs/04-05_21-50/results/synthesis/picorv32a.synthesis_cts.v
read_liberty $::env(LIB_SYNTH_COMPLETE)
link_design picorv32a
read_sdc /openLANE_flow/designs/picorv32a/src/my_base.sdc
set_propagated_clock [all_clocks]
report_checks -path_delay min_max -fields {slew trans net cap input_pins} -format full_clock_expanded -digits 4
report_clock_skew -hold
report_clock_skew -setup
After completion of CTS, now we need to lay down power distribution network(PDN) for the design and it is done by using the command gen_pdn .
We can clearly see that "PDN generation was succesful".
In the above figure we can see that the pitch of the standard cell rails is 2.720, which we have expected.
In the above figure we can observe the path through which power is delivered all the way to standard cells.
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The blocks that we can observe around the design are I/o pads and those with Red and Blue colours are Power Pads. Red pad is for power and the Blue one is for Gnd.
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Those blocks are connected to Power and Gnd Rings, which go around the design and supply power to straps.
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The vertical connections that we can observe for the rings are called Power Straps.
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From Power straps and Rings connections will be made to the Power rails. The standard cell will be placed in between these power rails. The height of the standard cells should be the multiples of the pitch of the rails in order to get power and gnd supplies accurately.
This is the overview of the PDN structure.
The Final stage in the flow is ROUTING. we can start routing by using the command run_routing .
From tha above figures we can see that routing is done and it is done with 0 violations, So our routing is succesful but we can see the negative slack. We need to eliminate that negative slack for succesful completion of Physical design flow.
We can see the final layout in gui using magic tool by using the command
magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/04-05_21-50/tmp/merged.lef def read /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/04-05_21-50/results/routing/picorv32a.def &
- https://github.com/nickson-jose/vsdstdcelldesign
- https://github.com/google/skywater-pdk
- https://github.com
- Material provided in workshop