auto generate verilog testbench file
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README.md

README.md

AutoTestbench

A very simple plugin to generate verilog testbench file, component instance current design unit and others.

I hope you like it.

Feature

  • Generate testbench templet

  • Generate component instance

  • Support verilog-2001 syntax

Recommend module(port) declaration

module spi_slave_core
(
    input  wire                 clk,
    input  wire                 rst,

    input  wire                 spi_cs,
    input  wire                 spi_clk,
    input  wire                 spi_mosi,
    output  reg                 spi_miso,

    input  wire                 spi_dummy,
    input  wire [7:0]           spi_tx_data,

    output  reg                 spi_oe,
    output  reg [7:0]           spi_rx_data
);

Note

  1. Don't support port declaration like below:
intput      a,
b, c ;
intput      a, b, c, d;
  1. parameter declaration must like below(don't use space):
module Top #
(
  parameter SATA_BURST_SIZE     = 32'd16*1024
)
(
    input   xxx,
    output  xxx
);
  1. This plugin don't check your syntax whether is corrected. It only find port declaration, you should invoke compiler to do it before use this plugin.

Usage

This plugin is very easy to use.

  • Run ,tb (or :TestBench in command line) to generate a testbench Also you can define other maps to invoke it.

  • Run ,in (or :Instance in command line) to generate component instance, and use p to paste it.

Installation

  • Clone the plugin into a separate directory:

$ cd ~/vimfiles/bundle

$ git clone https://github.com/kdurant/verilog-testbench.git verilog-testbench

or

Plug 'kdurant/verilog-testbench'

Configuration

  • let g:testbench_suffix = 'Tb' You can set testbench module name suffix with g:testbench_suffix

Contributions

Contributions, issue and pull requests are welcome