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auto generate verilog testbench file
Branch: master

remove trailing char

latest commit acb566a8dc
kdurant authored
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plugin remove trailing char


A very simple plugin to generate verilog testbench file, component instance current design unit and others. I hope you like it.


  • Auto generate testbench about current file

  • Auto generate component instance about current file

  • Support verilog-2001 syntax

  • Support port declaration like below(up to four):

    intput a, b, c, d;

  • Don't support port declaration like below:

    intput a, b, c ;

  • Rapid input verilog port, reg and wire demo

  • This plugin don't check your syntax whether is corrected. You should invoke compiler to do it before use this plugin.


This plugin is very easy to use.

  • Run ,tb (or :TestBench in command line) to generate a testbench and will display it in current window. Also you can define other maps to invoke it.

  • Run ,in (or :Instance in command line) to generate component instance, and use p to paste it.

  • Run :InsertPort in command line to rapid input. Also, you can map it like below:

    imap :InsertPort



  • Set this to 1 to load file header like below: /*============================================================================= # FileName : SPImasterTb.v # Author : autor # Email : # Description : # Version : V1.0 # LastChange : 2013-08-21 # ChangeLog : \=============================================================================*/

    default: let g:testbench_load_header = 1

  • If you g:testbench_load_header is 1, you should set these variables: let g:vimrc_author='your name' let g:vimrc_email='your email'

    default: let g:vimrc_author = 'author' let g:vimrc_email = ''

  • You can set testbench module name suffix with g:testbench_suffix default: let g:testbench_suffix = 'Tb'

  • You can set suqare brackets part width default: let g:testbench_bracket_width = 12


Contributions, issue and pull requests are welcome

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