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mempool/octeontx2: optimize for L1D cache architecture
OCTEON TX2 has 8 sets, 41 ways L1D cache, VA<9:7> bits dictate the set selection. Add additional padding to ensure that the element size always occupies odd number of cachelines to ensure even distribution of elements among L1D cache sets. Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com> Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com> Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
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