net/hns3: support new device

[ upstream commit 3f1436d7006c2659232305ef2b8b186796319041 ] This patch introduces the new devices, which are on-chip network interface controllers with RDMA/DCB/ROH supporting. One is 100GE and the other is 200GE. Both can be found on HIP09/HIP10 SoCs. Signed-off-by: Jie Hai <haijie1@huawei.com>
kevintraynor · Apr 3, 2024 · 95826da · 95826da
1 parent 300a10e
commit 95826da
Show file tree

Hide file tree

Showing 4 changed files with 8 additions and 2 deletions.
diff --git a/doc/guides/nics/hns3.rst b/doc/guides/nics/hns3.rst
@@ -6,7 +6,7 @@ HNS3 Poll Mode Driver
 
 The hns3 PMD (**librte_net_hns3**) provides poll mode driver support
 for the inbuilt HiSilicon Network Subsystem(HNS) network engine
-found in the HiSilicon Kunpeng 920 SoC and Kunpeng 930 SoC .
+found in the HiSilicon Kunpeng 920 SoC (HIP08) and Kunpeng 930 SoC (HIP09/HIP10).
 
 Features
 --------

diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c
@@ -543,7 +543,9 @@ hns3_set_dcb_capability(struct hns3_hw *hw)
 	if (device_id == HNS3_DEV_ID_25GE_RDMA ||
 	    device_id == HNS3_DEV_ID_50GE_RDMA ||
 	    device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
-	    device_id == HNS3_DEV_ID_200G_RDMA)
+	    device_id == HNS3_DEV_ID_200G_RDMA ||
+	    device_id == HNS3_DEV_ID_100G_ROH ||
+	    device_id == HNS3_DEV_ID_200G_ROH)
 		hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
 }
 

diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c
@@ -6713,6 +6713,8 @@ static const struct rte_pci_id pci_id_hns3_map[] = {
 	{ RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
 	{ RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
 	{ RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
+	{ RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_ROH) },
+	{ RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_ROH) },
 	{ .vendor_id = 0, }, /* sentinel */
 };
 

diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h
@@ -28,7 +28,9 @@
 #define HNS3_DEV_ID_25GE_RDMA			0xA222
 #define HNS3_DEV_ID_50GE_RDMA			0xA224
 #define HNS3_DEV_ID_100G_RDMA_MACSEC		0xA226
+#define HNS3_DEV_ID_100G_ROH	                0xA227
 #define HNS3_DEV_ID_200G_RDMA			0xA228
+#define HNS3_DEV_ID_200G_ROH	                0xA22C
 #define HNS3_DEV_ID_100G_VF			0xA22E
 #define HNS3_DEV_ID_100G_RDMA_PFC_VF		0xA22F