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net/hns3: fix Rx multiple firmware reset interrupts
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[ upstream commit e3c71325cec3353c4b9623310ece363a7c79604f ]

In the firmware (also known as IMP) reset scenario, driver interrupt
processing and firmware watchdog initialization are asynchronous.

If the driver interrupt processing is faster than firmware watchdog
initialization (that is, the driver clears the firmware reset
interrupt source before the firmware watchdog is initialized), the
driver will receive multiple firmware reset interrupts.

In the Kunpeng 920 platform, the above situation does not exist. But
it does on the newer platforms. So we add 5ms delay before drivers
clears the IMP reset interrupt source.

As for the impact of 5ms, the number of PFs managed by a firmware is
limited. Therefore, even if a DPDK process takes over all the PFs
which managed by the firmware, the delay is controllable.

Fixes: ee930d3 ("net/hns3: fix timing of clearing interrupt source")

Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
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fengchengwen authored and kevintraynor committed Jul 11, 2023
1 parent 5c10505 commit b374bc7
Showing 1 changed file with 14 additions and 0 deletions.
14 changes: 14 additions & 0 deletions drivers/net/hns3/hns3_ethdev.c
Original file line number Diff line number Diff line change
Expand Up @@ -286,6 +286,19 @@ hns3_handle_mac_tnl(struct hns3_hw *hw)
}
}

static void
hns3_delay_before_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
{
#define IMPRESET_WAIT_MS_TIME 5

if (event_type == HNS3_VECTOR0_EVENT_RST &&
regclr & BIT(HNS3_VECTOR0_IMPRESET_INT_B) &&
hw->revision >= PCI_REVISION_ID_HIP09_A) {
rte_delay_ms(IMPRESET_WAIT_MS_TIME);
hns3_dbg(hw, "wait firmware watchdog initialization completed.");
}
}

static void
hns3_interrupt_handler(void *param)
{
Expand All @@ -305,6 +318,7 @@ hns3_interrupt_handler(void *param)
vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
hns3_delay_before_clear_event_cause(hw, event_cause, clearval);
hns3_clear_event_cause(hw, event_cause, clearval);
/* vector 0 interrupt is shared with reset and mailbox source events. */
if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
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