Skip to content

Commit

Permalink
net/mlx5: fix check for orphan wait descriptor
Browse files Browse the repository at this point in the history 
[ upstream commit 37d6fc3 ]

The mlx5 PMD supports send scheduling feature, it allows
to send packets at specified moment of time, to do that
PMD pushes special wait descriptor (WQE) to the hardware
queue and then pushes descriptor for packet data as usual.
If queue is close to be full or there is no enough elts
buffers to store mbufs being sent the data descriptors might
be not pushed and the orphan wait WQE (not followed by the
data) might reside in queue on tx_burst routine exit.

To avoid orphan wait WQEs there was the check for enough
free space in the queue WQE buffer and enough amount of the
free elts in queue mbuf storage. This check was incomplete
and did not cover all the cases for Enhanced Multi-Packet
Write descriptors.

Fixes: 2f827f5 ("net/mlx5: support scheduling on send routine template")

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
  • Loading branch information
@viacheslavo @kevintraynor
viacheslavo authored and kevintraynor committed Oct 11, 2022
1 parent 879ebb7 commit b5e5d92
Showing 1 changed file with 41 additions and 33 deletions.
74 changes: 41 additions & 33 deletions drivers/net/mlx5/mlx5_tx.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1622,6 +1622,7 @@ mlx5_tx_mseg_build(struct mlx5_txq_data *__rte_restrict txq,
static __rte_always_inline enum mlx5_txcmp_code
mlx5_tx_schedule_send(struct mlx5_txq_data *restrict txq,
struct mlx5_txq_local *restrict loc,
uint16_t elts,
unsigned int olx)
{
if (MLX5_TXOFF_CONFIG(TXPP) &&
Expand All @@ -1636,7 +1637,7 @@ mlx5_tx_schedule_send(struct mlx5_txq_data *restrict txq,
* to the queue and we won't get the orphan WAIT WQE.
*/
if (loc->wqe_free <= MLX5_WQE_SIZE_MAX / MLX5_WQE_SIZE ||
loc->elts_free < NB_SEGS(loc->mbuf))
loc->elts_free < elts)
return MLX5_TXCMP_CODE_EXIT;
/* Convert the timestamp into completion to wait. */
ts = *RTE_MBUF_DYNFIELD(loc->mbuf, txq->ts_offset, uint64_t *);
Expand Down Expand Up @@ -1666,6 +1667,9 @@ mlx5_tx_schedule_send(struct mlx5_txq_data *restrict txq,
* Pointer to TX queue structure.
* @param loc
* Pointer to burst routine local context.
* @param elts
* Number of free elements in elts buffer to be checked, for zero
* value the check is optimized out by compiler.
* @param olx
* Configured Tx offloads mask. It is fully defined at
* compile time and may be used for optimization.
Expand All @@ -1683,11 +1687,12 @@ mlx5_tx_packet_multi_tso(struct mlx5_txq_data *__rte_restrict txq,
struct mlx5_wqe *__rte_restrict wqe;
unsigned int ds, dlen, inlen, ntcp, vlan = 0;

MLX5_ASSERT(loc->elts_free >= NB_SEGS(loc->mbuf));
if (MLX5_TXOFF_CONFIG(TXPP)) {
enum mlx5_txcmp_code wret;

/* Generate WAIT for scheduling if requested. */
wret = mlx5_tx_schedule_send(txq, loc, olx);
wret = mlx5_tx_schedule_send(txq, loc, 0, olx);
if (wret == MLX5_TXCMP_CODE_EXIT)
return MLX5_TXCMP_CODE_EXIT;
if (wret == MLX5_TXCMP_CODE_ERROR)
Expand Down Expand Up @@ -1781,11 +1786,12 @@ mlx5_tx_packet_multi_send(struct mlx5_txq_data *__rte_restrict txq,
unsigned int ds, nseg;

MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
MLX5_ASSERT(loc->elts_free >= NB_SEGS(loc->mbuf));
if (MLX5_TXOFF_CONFIG(TXPP)) {
enum mlx5_txcmp_code wret;

/* Generate WAIT for scheduling if requested. */
wret = mlx5_tx_schedule_send(txq, loc, olx);
wret = mlx5_tx_schedule_send(txq, loc, 0, olx);
if (wret == MLX5_TXCMP_CODE_EXIT)
return MLX5_TXCMP_CODE_EXIT;
if (wret == MLX5_TXCMP_CODE_ERROR)
Expand Down Expand Up @@ -1896,16 +1902,7 @@ mlx5_tx_packet_multi_inline(struct mlx5_txq_data *__rte_restrict txq,

MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
if (MLX5_TXOFF_CONFIG(TXPP)) {
enum mlx5_txcmp_code wret;

/* Generate WAIT for scheduling if requested. */
wret = mlx5_tx_schedule_send(txq, loc, olx);
if (wret == MLX5_TXCMP_CODE_EXIT)
return MLX5_TXCMP_CODE_EXIT;
if (wret == MLX5_TXCMP_CODE_ERROR)
return MLX5_TXCMP_CODE_ERROR;
}
MLX5_ASSERT(loc->elts_free >= NB_SEGS(loc->mbuf));
/*
* First calculate data length to be inlined
* to estimate the required space for WQE.
Expand Down Expand Up @@ -2011,6 +2008,16 @@ mlx5_tx_packet_multi_inline(struct mlx5_txq_data *__rte_restrict txq,
* supposing no any mbufs is being freed during inlining.
*/
do_build:
if (MLX5_TXOFF_CONFIG(TXPP)) {
enum mlx5_txcmp_code wret;

/* Generate WAIT for scheduling if requested. */
wret = mlx5_tx_schedule_send(txq, loc, 0, olx);
if (wret == MLX5_TXCMP_CODE_EXIT)
return MLX5_TXCMP_CODE_EXIT;
if (wret == MLX5_TXCMP_CODE_ERROR)
return MLX5_TXCMP_CODE_ERROR;
}
MLX5_ASSERT(inlen <= txq->inlen_send);
ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
MLX5_ESEG_MIN_INLINE_SIZE +
Expand Down Expand Up @@ -2171,7 +2178,7 @@ mlx5_tx_burst_tso(struct mlx5_txq_data *__rte_restrict txq,
enum mlx5_txcmp_code wret;

/* Generate WAIT for scheduling if requested. */
wret = mlx5_tx_schedule_send(txq, loc, olx);
wret = mlx5_tx_schedule_send(txq, loc, 1, olx);
if (wret == MLX5_TXCMP_CODE_EXIT)
return MLX5_TXCMP_CODE_EXIT;
if (wret == MLX5_TXCMP_CODE_ERROR)
Expand Down Expand Up @@ -2549,16 +2556,6 @@ mlx5_tx_burst_empw_simple(struct mlx5_txq_data *__rte_restrict txq,

next_empw:
MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
if (MLX5_TXOFF_CONFIG(TXPP)) {
enum mlx5_txcmp_code wret;

/* Generate WAIT for scheduling if requested. */
wret = mlx5_tx_schedule_send(txq, loc, olx);
if (wret == MLX5_TXCMP_CODE_EXIT)
return MLX5_TXCMP_CODE_EXIT;
if (wret == MLX5_TXCMP_CODE_ERROR)
return MLX5_TXCMP_CODE_ERROR;
}
part = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
MLX5_MPW_MAX_PACKETS :
MLX5_EMPW_MAX_PACKETS);
Expand All @@ -2569,6 +2566,16 @@ mlx5_tx_burst_empw_simple(struct mlx5_txq_data *__rte_restrict txq,
/* But we still able to send at least minimal eMPW. */
part = loc->elts_free;
}
if (MLX5_TXOFF_CONFIG(TXPP)) {
enum mlx5_txcmp_code wret;

/* Generate WAIT for scheduling if requested. */
wret = mlx5_tx_schedule_send(txq, loc, 0, olx);
if (wret == MLX5_TXCMP_CODE_EXIT)
return MLX5_TXCMP_CODE_EXIT;
if (wret == MLX5_TXCMP_CODE_ERROR)
return MLX5_TXCMP_CODE_ERROR;
}
/* Check whether we have enough WQEs */
if (unlikely(loc->wqe_free < ((2 + part + 3) / 4))) {
if (unlikely(loc->wqe_free <
Expand Down Expand Up @@ -2723,23 +2730,23 @@ mlx5_tx_burst_empw_inline(struct mlx5_txq_data *__rte_restrict txq,
unsigned int slen = 0;

MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
/*
* Limits the amount of packets in one WQE
* to improve CQE latency generation.
*/
nlim = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
MLX5_MPW_INLINE_MAX_PACKETS :
MLX5_EMPW_MAX_PACKETS);
if (MLX5_TXOFF_CONFIG(TXPP)) {
enum mlx5_txcmp_code wret;

/* Generate WAIT for scheduling if requested. */
wret = mlx5_tx_schedule_send(txq, loc, olx);
wret = mlx5_tx_schedule_send(txq, loc, nlim, olx);
if (wret == MLX5_TXCMP_CODE_EXIT)
return MLX5_TXCMP_CODE_EXIT;
if (wret == MLX5_TXCMP_CODE_ERROR)
return MLX5_TXCMP_CODE_ERROR;
}
/*
* Limits the amount of packets in one WQE
* to improve CQE latency generation.
*/
nlim = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
MLX5_MPW_INLINE_MAX_PACKETS :
MLX5_EMPW_MAX_PACKETS);
/* Check whether we have minimal amount WQEs */
if (unlikely(loc->wqe_free <
((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
Expand Down Expand Up @@ -3022,11 +3029,12 @@ mlx5_tx_burst_single_send(struct mlx5_txq_data *__rte_restrict txq,
enum mlx5_txcmp_code ret;

MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
MLX5_ASSERT(loc->elts_free);
if (MLX5_TXOFF_CONFIG(TXPP)) {
enum mlx5_txcmp_code wret;

/* Generate WAIT for scheduling if requested. */
wret = mlx5_tx_schedule_send(txq, loc, olx);
wret = mlx5_tx_schedule_send(txq, loc, 0, olx);
if (wret == MLX5_TXCMP_CODE_EXIT)
return MLX5_TXCMP_CODE_EXIT;
if (wret == MLX5_TXCMP_CODE_ERROR)
Expand Down

0 comments on commit b5e5d92

Please sign in to comment.